View AM53CF96JCW_3264765.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this document contains information on a product under development at advanced micro devices inc. the information is intended to help you to evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 17348 rev. b amendment /0 issue date: may 1993 advanced micro devices am53cf94/am53cf96 enhanced scsi-2 controller (esc) preliminary distinctive characteristics n pin/function compatible with emulex fas216/236 n amd's patented programmable glitch eater tm circuitry on req and ack inputs n 10 mbytes/s synchronous fast scsi transfer rate n 20 mbytes/s dma transfer rate n 16-bit dma interface plus 2 bits of parity n flexible three bus architecture n single-ended scsi bus supported by am53cf94 n differential scsi bus supported by am53cf96 n selection of multiplexed or non-multiplexed address and data bus n high current drivers (48 ma) for direct connection to the single-ended scsi bus n supports disconnect and reselect commands n supports burst mode dma operation with a threshold of eight n supports 3-byte tagged-queueing as per the scsi-2 specification n supports group 2 and 5 command recognition as per the scsi-2 specification n advanced cmos process for lower power consumption n amd's exclusive programmable power-down feature n 24-bit extended transfer counter allows for data block transfer of up to 16 mbytes n independently programmable 3-byte message and group 2 identification n additional check for id message during bus-initiated select with atn n reselection has qtag features of atn 3 n access fifo command n delayed enable signal for differential drivers avoid contention on scsi differential lines n programmable active negation on req , ack and data lines n register programmable control of assertion/ deassertion delay for req and ack lines n part-unique id code n am53cf94 available in 84-pin plcc package n am53cf96 available in 100-pin pqfp package n am53cf94 available in 3.3 v version n supports clock operating frequencies from 10 mhzC40 mhz n supports scatter-gather or back-to-back synchronous data transfers general description the enhanced scsi-2 controller (esc) was designed to support fast scsi-2 transfer rates of up to 10 mbytes/s in synchronous mode and up to 7 mbytes/s in the asynchronous mode. the esc is downward com- patible with the am53c94/96, combining its functionality with features such as fast scsi, programmable active negation, a 24-bit transfer counter, and a part-unique id code containing manufacturer and serial # information. amds proprietary features such as power-down mode for scsi transceivers, programmable glitch eater, and extended target command set are also included for improved product performance. the enhanced scsi-2 controller (esc) has a flexible three bus architecture. the esc has a 16-bit dma inter- face, an 8-bit host data interface and an 8-bit scsi data interface. the esc is designed to minimize host inter- vention by implementing common scsi sequences in hardware. an on-chip state machine reduces protocol overheads by performing the required sequences in re- sponse to a single command from the host. selection, reselection, information transfer and disconnection commands are directly supported. the 16-byte-internal fifo further assists in minimizing host involvement. the fifo provides a temporary stor- age for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit scsi data bus. during dma operations the fifo acts as a buffer to allow greater latency in the dma channel. this permits the dma channel to be sus- pended for higher priority operations such as dram re- fresh or reception of an isdn packet. parity on the dma bus is optional. parity can either be generated and checked or it can be simply passed through. the target command set for the am53cf94/96 in- cludes an additional command, the access fifo com- mand, to allow the host or dma controller to remove re- maining fifo data following the hosts issuance of a target abort dma command or following an abort due to
p r e l i m i n a r y amd 2 am53cf94/am53cf96 parity error. this command facilitates data recovery and thereby minimizes the need to re-transmit data. amds exclusive power-down feature can be enabled to help reduce power consumption during the chips sleep mode. the receivers on the scsi bus may be turned off to eliminate current that may flow because termination power (~3 v) is close to the trip point of the input buffers. the patented glitch eater circuitry in the enhanced scsi-2 controller can be programmed to filter glitches with widths up to 35 ns. it is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. the glitch eater circuitry is implemented on the ack and req lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. such signal inconsistencies can trigger false req / ack handshaking, false data transfers, addition of random data, and double clocking. amds glitch eater circuitry therefore maintains system perform- ance and improves reliability. the following diagram illustrates this circuits operation. the am53cf94 is also available in a 3.3 v version. scsi environment device without the glitch eater circuit amds device with the glitch eater circuit glitch eater circuitry in scsi environment note: the glitch window is programmable via control register four (0dh), bits 6 & 7. window may be set to 35 ns (max). default setting is 12 ns (single-ended). 17348b-1 glitch window system block diagram 9 cpu dma memory am53cf94/96 8 16 16 4 9 scsi data 16 dma addr data scsi control 16 17348b-2
p r e l i m i n a r y amd 3 am53cf94/am53cf96 system bus mode diagrams 8-bit data bus address bus dma controller host processor am53cf94/96 bus controller dma 7C0 a 3C0 rd wr dmawr busmd 0 busmd 1 dreq dack bus mode 0 single bus architecture: 8-bit dma, 8-bit processor 17348b-3 data bus address bus rd wr dmawr dreq dack dma controller host processor am53cf94/96 bus controller dma 15C0 a 3C0 busmd 0 busmd 1 8 16 v dd bus mode 1 single bus architecture: 16-bit dma, 8-bit processor 17348b-4
p r e l i m i n a r y amd 4 am53cf94/am53cf96 system bus mode diagrams dmard v dd 8-bit data bus dma controller host processor am53cf94/96 dma 15C0 ad 7C0 wr dmawr busmd 0 busmd 1 dreq dack rd bhe as0 ale 16-bit data bus bus mode 2 dual bus architecture: 16-bit dma with byte control, 8-bit multiplexed processor address data 17348b-5 v dd address bus dma controller host processor am53cf94/96 dma 15C0 a 3C0 wr dmawr busmd 0 busmd 1 dreq dack rd 16-bit data bus 8-bit data bus ad 7C0 bus mode 3 dual bus architecture: 16-bit dma, 8-bit processor 17348b-6
p r e l i m i n a r y amd 5 am53cf94/am53cf96 block diagram 17348b-7 bus interface unit 18 18 16 x 9 fifo (including parity) parity logic data tranceivers scsi control mux 8 8 8 9 clk 6 4 dma 15-0 dmap 1-0 dma control ad 7-0 host control busmd 1-0 reset cs 9 scsi control scsi bus data + parity (single ended) main sequencer scsi sequencer register bank dfmode 9 scsi bus data + parity direction control 7 scsi control direction control
p r e l i m i n a r y amd 6 am53cf94/am53cf96 connection diagrams top view 17348b-8 dma11 dma10 dma9 dma8 dma7 dma3 dma2 dma1 dma0 dma4 dmap0 dmap1 dma14 dma13 dma12 dma15 dma5 dma6 ad3 ad2 ad1 ad0 clk ale [a3] dmard [a2] bhe [a1] as0 [a0] ad4 ad5 dreq dack dmawr ad6 ad7 cs rd wr bsyc reqc msg c/d i/o atn rstc sel bsy req ack rst busmd 0 int reset selc busmd 1 ackc 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 59 58 57 56 55 54 60 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 111098765432184838281807978777675 am53cf94 84-pin plcc sd 6 sd 7 sd p v dd vss v ss sd 3 sd 4 sd 5 sd 0 sd 1 sd 2 sdc 3 sdc 0 sdc 1 sdc 2 sdc 6 sdc 7 sdc p sdc 4 sdc 5 v dd v ss v ss v ss v ss v ss v ss v ss nc isel tsel dma0 dma1 dma2 dma3 dma4 dma5 dma6 dma7 dmap0 dma8 dma9 dma10 dma11 dma12 dma13 dma14 dma15 dmap1 nc sd 0 sd 1 dack dmawr nc sdc 7 sdc p busmd 0 busmd 1 rst ack req sel atn i/o c/d msg ackc reqc bsyc v ss rstc bsy rd nc reset int wr selc v ss nc sdc 6 cs as0 [a0] bhe [a1] dmard [a2] ale [a3] clk dfmode nc ad0 ad1 ad2 ad3 v ss v ss ad4 ad5 ad6 ad7 dreq v ss v ss v ss v ss v ss v ss v dd v dd sdc 0 sdc 1 sdc 2 sdc 3 sdc 4 sdc 5 sd 2 sd 3 v ss v ss sd 4 sd 5 sd 6 sd 7 sd p v ss v ss 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 49 50 44 am53cf96 100-pin pqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 29 1 23 45678910111213141516171819202122232425262728 30 52 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 51 v ss v ss 17348b-9
p r e l i m i n a r y amd 7 am53cf94/am53cf96 logic symbol sdc p busmd 1C0 * dfmode int cs wr rd am53cf94/96 sd 7C0 sd p bsyc msg c/d i/o atn selc rstc reqc ackc sdc 7C0 bsy sel rst req ack * isel * tsel dma 15C0 dmap 1C0 dreq bhe [a1] as0 [a0] ale [a3] ad 7C0 dmard [a2] dack dmawr clk reset note: *pins available on the am53cf96 only. 17348b-10 related amd products part number description 85c30 enhanced serial communication controller 26lsxx line drivers/receivers 33c93a enhanced cmos scsi bus interface controller 80c186 highly integrated 16-bit microprocessor 80c286 high-performance 16-bit 80286 microprocessor part number description am386 tm high-performance 32-bit microprocessor 53c80a scsi bus controller 80188 highly integrated 8-bit microprocessor 85c80 combination 53c80a scsi and 85c30 escc 53c94lv low voltage, high performance scsi controller
p r e l i m i n a r y amd 8 am53cf94/am53cf96 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c = commercial package type j = 84-pin plcc (pl 084) k = 100-pin metric pqfp (pqr100) device number/description am53cf94/am53cf96 enhanced scsi-2 controller am53cf94 am53cf96 am53cf96 k c valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the lo- cal amd sales office to confirm availability of specific valid combinations or to check on newly released combinations. jc kc, kc/w valid combinations alternate packaging option /w = trimmed and formed in a tray blank = molded carrier ring (36 mm) /w
p r e l i m i n a r y amd 9 am53cf94/am53cf96 scsi output connections am53cf94 am53cf94 single ended scsi bus configuration sdc 7C0, p selc , bsyc , reqc , ackc , rstc sd 7C0, p sel , bsy , req , ack , rst msg , c/d , i/o , atn 17348b-11
p r e l i m i n a r y amd 10 am53cf94/am53cf96 scsi output connections am53cf96 am53cf96 single ended scsi bus configuration sdc 7C0, p selc , bsyc , reqc , ackc , rstc sd 7C0, p sel , bsy , req , ack , rst msg , c/d , i/o , atn dfmode v cc 17348b-12 sdc 7C0, p selc , bsyc , rstc sd 7C0, p sel , bsy , rst msg , c/d , i/o , req dfmode atn , ack am53cf96 differential scsi bus configuration tsel isel am53cf96 dt dt dt dt 17348b-13
p r e l i m i n a r y amd 11 am53cf94/am53cf96 tsel vcc differential transceiver connections for the differential scsi bus configuration using 75als170 and 75als171 transceivers vcc selc gnd sel + sel C sel bsyc gnd bsy + bsy C bsy rstc gnd rst + rst C rst gnd 75als171 sdc 6 sd 6 C sd 6 + sd 6 sdc 7 sd 7 C sd 7 + sd 7 sdc p sd p C sd p + sd p 75als170 sdc 3 sd 3 C sd 3 + sd 3 sdc 4 sd 4 C sd 4 + sd 4 sdc 5 sd 5 C sd 5 + sd 5 75als170 sdc 0 sd 0 C sd 0 + sd 0 sdc 1 sd 1 C sd 1 + sd 1 sdc 2 sd 2 C sd 2 + sd 2 75als170 atn isel C atn + atn 75als170 C msg + msg C c/d tsel msg tsel c/d + c/d tsel i/o C i/o + i/o 75als170 reqc ackc req + req C req isel ack + ack C ack 75als171 gnd 17348b-14
p r e l i m i n a r y amd 12 am53cf94/am53cf96 sdc 6 sd 6 differential transceiver connections for the differential scsi bus configuration using 75176a transceiver C sd 6 + sd 6 sd 6 sdc 6 rstc gnd rst + rst C rst gnd sdc 0 sd 0 C sd 0 + sd 0 sdc 0 sd 0 tsel msg C msg + msg msg tsel sdc 1 sd 1 C sd 1 + sd 1 sd 1 sdc 1 tsel c/d C c/d + c/d c/d tsel sdc 2 sd 2 C sd 2 + sd 2 sd 2 sdc 2 tsel i/o C i/o + i/o i/o tsel sdc 3 sd 3 C sd 3 + sd 3 sd 3 sdc 3 isel atn C atn + atn atn isel sdc 4 sd 4 C sd 4 + sd 4 sd 4 sdc 4 selc gnd sel + sel C sel gnd sdc 5 sd 5 C sd 5 + sd 5 sd 5 sdc 5 bsyc gnd bsy + bsy C bsy gnd sdc 7 sd 7 C sd 7 + sd 7 sd 7 sdc 7 tsel reqc req + req C req gnd sdc p sd p C sd p + sd p sd p sdc p isel ackc ack + ack C ack gnd 17348b-15
p r e l i m i n a r y amd 13 am53cf94/am53cf96 pin description host interface signals dma 15C0 data/dma bus (input/output, active high, internal pull-up) the configuration of this bus depends on the bus mode 1C0 (busmd 1C0) inputs. when the device is config- ured for single bus operation, the host can access the internal register set on the lower eight lines while dma accesses can be made to the fifo using the entire bus. when using the byte mode via the bhe and a0 inputs the data can be transferred on either the upper or lower half of the dma 15C0 bus. dmap 1C0 data/dma parity bus (input/output, active high, internal pull-up) these lines are odd parity for the dma 15C0 bus. dmap 1 is the parity for the upper half of the bus (dma 15C8) and dmap 0 is the parity for the lower half of the bus (dma 7C0). ale [a3] address latch enable [address 3] (input, active high) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as ale. as ale, this input latches the address on the ad 7C0 bus on its low going edge. when the device is configured for all other bus modes, this input acts as a3. as a3, this input is the third bit of the address bus. dmard [a2] dma read [address 2] (input, active low [active high]) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as dmard . as dmard , this input is the read signal for the dma 15C0 bus. when the device is configured for all other bus modes, this in- put acts as a2. as a2, this input is the second bit of the address bus. bhe [a1] bus high enable [address 1] (input, active high) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as bhe. as bhe, this input works in conjunction with as0 to indicate the lines on which data transfer will take place. when the device is configured for all other bus modes this input acts as a1. as a1, this input is the first bit of the address bus. as0 [a0] address status [address 0] (input, active high) this is a dual function input. when the device is config- ured for the dual bus mode (two buses, multiplexed and byte control), this input acts as as0. as as0, this input works in conjunction with bhe to indicate the lines on which data transfer will take place. when the device is configured for all other bus modes, this input acts as a0. as a0, this input is the zeroth bit of the address bus. the following is the decoding for the bhe and as0 inputs: bhe as0 bus used 1 1 upper bus C dma 15C8, dmap 1 1 0 full bus C dma 15C0, dmap 1C0 0 1 reserved 0 0 lower bus C dma 7C0, dmap 0 dreq dma request (output, active high, hi-z) this output signal to the dma controller will be active during dma read and write cycles. during a dma read cycle it will be active as long as there is a word (or a byte in the byte mode) in the fifo to be transferred to mem- ory. during a dma write cycle it will be active as long as there is an empty space for a word (or a byte in mode 2) in the fifo. dack dma acknowledge (input, active low) this input signal from the dma controller will be active during dma read and write cycles. the dack signal is used to access the dma fifo only and should never be active simultaneously with the cs signal, which ac- cesses the registers only. ad 7C0 host address data bus (input/output, active high, internal pull-up) this bus is used only in the dual bus mode. this bus al- lows the host processor to access the devices internal registers while the dma bus is transferring data. when using multiplexed bus, these lines can be used for ad- dress and data. when using non multiplexed bus these lines can be used for the data only.
p r e l i m i n a r y amd 14 am53cf94/am53cf96 dmawr dma write (input, active low) this signal writes the data onto the dma 15C0 and dmap 1C0 bus into the internal fifo when dack is also active. when in the single bus mode this signal must be tied to the wr signal. rd read (input active low) this signal reads the internal device registers and places their contents on the data bus, when either cs signal or dack signal is active. wr write (input active low) this signal writes the internal device registers with the value present on the (ad 7C0 bus or the dma 15C0 and dmap 1C0 bus), when the cs signal is also active. cs chip select (input active low) this signal enables the read and write of the device reg- isters. cs enables access to any register (including the fifo) while the dack enables access only to the fifo. cs and dack should never be active simultaneously in the single bus mode, they may however be active simul- taneously in the dual bus mode provided the cs signal is not enabling access to the fifo. int interrupt (output, active low, open drain) this signal is a non-maskable interrupt flag to the host processor. this signal is latched on the output on the high going edge of the clock. this flag may be cleared by reading the interrupt status register (istat) or by per- forming a device reset (hard or soft). this flag is not cleared by a scsi reset. dfmode differential mode (input, active low) this input is available only on the am53cf96. this input configures the scsi bus to either single ended or differ- ential mode. when this input is active, the device oper- ates in the differential scsi mode. the scsi data is available on the sd 7C0 lines and the high active trans- ceiver enables on the sdc 7C0 outputs. when this input is inactive, the device operates in the single ended scsi mode. the scsi input data is available on sd 7C0 lines and the output data is available on sdc 7C0 lines. in the single ended scsi mode, the sd 7C0 and the sdc 7C0 buses can be tied together externally. busmd 1C0 bus mode (input, active high) these inputs configure the device for single bus or dual bus operation and the dma bus width. busmd1 busmd0 bus configuration 1 1 two buses: 8-bit host bus and 16-bit dma bus register address on a 3C0 and data on ad bus 1 0 two buses: multiplexed and byte control register address on ad 3C0 and data on ad bus 0 1 single bus: 8-bit host bus and 16-bit dma bus register address on a 3C0 and data on dma bus 0 0 single bus: 8-bit host bus and 8-bit dma bus register address on a 3C0 and data on dma bus clk clock (input) clock input used to generate all the internal device tim- ings. the maximum frequency of this input is 40 mhz. and a minimum of 10 mhz to maintain the scsi bus timings. reset reset (input, active high) this input when active resets the device. the reset in- put must be active for at least two clk periods after the voltage on the power inputs have reached vcc minimum. scsi interface signals sd 7C0 scsi data (input/output, active low, schmitt trigger) when the device is configured in the single ended scsi mode ( dfmode inactive) these pins are defined as in- puts for the scsi data bus. when the device is config- ured in the differential scsi mode ( dfmode active) these pins are defined as bidirectional scsi data bus.
p r e l i m i n a r y amd 15 am53cf94/am53cf96 sd p scsi data parity (input/output, active low, schmitt trigger) when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as the input for the scsi data parity. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as bidirectional scsi data parity. sdc 7C0 scsi data control (output, active low, open drain) when the device is configured in the single ended scsi mode ( dfmode inactive) these pins are defined as out- puts for the scsi data bus. when the device is config- ured in the differential scsi mode ( dfmode active) these pins are defined as direction controls for the exter- nal differential transceivers. in this mode, a signal high state corresponds to an output to the scsi bus and a low state corresponds to an input from the scsi bus. sdc p scsi data control parity (output, active low, open drain) when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as an out- put for the scsi data parity. when the device is config- ured in the differential scsi mode ( dfmode active) this pin is defined as the direction control for the external differential transceiver. in this mode, a signal high state corresponds to an output to the scsi bus and a low state corresponds to an input from the scsi bus. msg message (input/output, active low, schmitt trigger) this is a bidirectional signal with 48 ma output driver. it is an output in the target mode and a schmitt trigger input in the initiator mode. c/d command/data (input/output, schmitt trigger) this is a bidirectional signal with 48 ma output driver. it is an output in the target mode and a schmitt trigger input in the initiator mode. i/o input/output (input/output, schmitt trigger) this is a bidirectional signal with 48 ma output driver. it is an output in the target mode and a schmitt trigger input in the initiator mode. atn attention (input/output, active low, schmitt trigger) this signal is a 48 ma output in the initiator mode and a schmitt trigger input in the target mode. this signal will be asserted when the initiator detects a parity error or it can be asserted via certain initiator commands. bsy busy (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. sel select (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. rst reset (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. req request (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. ack acknowledge (input, active low, schmitt trigger) this is a scsi input signal with a schmitt trigger. bsyc busy control (output, active low, open drain) this is a scsi output with 48 ma drive. when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as a bsy output for the scsi bus. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as the direction control for the external differential transceiver. in this mode, a signal high state corresponds to an out- put to the scsi bus and a low state corresponds to an input from the scsi bus. selc select control (output, active low, open drain) this is a scsi output with 48 ma drive. when the device is configured in the single ended scsi mode ( dfmode inactive) this pin is defined as a sel output for the scsi bus. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as the direction control for the external differential transceiver. in this mode, a signal high state corresponds to an out- put to the scsi bus and a low state corresponds to an input from the scsi bus.
p r e l i m i n a r y amd 16 am53cf94/am53cf96 rstc reset control (output, active low, open drain) this is a scsi output with 48 ma drive. the reset scsi command will cause the device to drive rstc active for 25 msC40 ms, which will depend on the clk frequency and the conversion factor. when the device is config- ured in the single ended scsi mode ( dfmode inac- tive) this pin is defined as a rst output for the scsi bus. when the device is configured in the differential scsi mode ( dfmode active) this pin is defined as the direc- tion control for the external differential transceiver. in this mode, a signal high state corresponds to an output to the scsi bus and a low state corresponds to an input from the scsi bus. reqc request control (output, active low, open drain) this is a scsi output with 48 ma drive. this signal is activated only in the target mode. ackc acknowledge control (output, active low, open drain) this is a scsi output with 48 ma drive. this signal is ac- tivated only in the initiator mode. isel initiator select (output, active high) this signal is available on the am53cf96 only. this sig- nal is active whenever the device is in the initiator mode. in the differential mode this signal is used to enable the initiator signals ackc and atn and the device also drives these signals. tsel target select (output, active high) this signal is available on the am53cf96 only. this sig- nal is active whenever the device is in the target mode. in the differential mode this signal is used to enable the target signals reqc , msg , c/d and i/o and the device also drives these signals. functional description register map address (hex.) operation register 00 read current transfer count register low 00 write start transfer count register low 01 read current transfer count register middle 01 write start transfer count register middle 02 read/write fifo register 03 read/write command register 04 read status register 04 write scsi destination id register 05 read interrupt status register 05 write scsi timeout register 06 read internal state register 06 write synchronous transfer period register address (hex.) operation register 07 read current fifo/internal state register 07 write synchronous offset register 08 read/write control register 1 09 write clock factor register 0a write forced test mode register 0b read/write control register 2 0c read/write control register 3 0d read/write control register 4 0e read current transfer count register high 0e write start transfer count register high 0f write data alignment register note: not all registers in this device are both readable and writable. some read only registers share the same address with write only registers. the registers can be accessed by asserting the cs signal and then asserting either rd or wr signal depending on the operation to be performed. only the fifo register can be accessed by asserting either cs or dack in conjunction with rd and wr signals or dmard and dmawr signals. the register address inputs are ignored when dack is used but must be valid when cs is used.
p r e l i m i n a r y amd 17 am53cf94/am53cf96 current transfer count register (00h, 01h, 0eh) read only current transfer count register ctcreg address: 00 h, 01 h, 0eh type: read 15 14 13 12 11 10 9 8 crvl15 crvl14 crvl13 crvl12 crvl11 crvl10 crvl9 crvl8 xxxxxxxx 76543210 crvl7 crvl6 crvl5 crvl4 crvl3 crvl2 crvl1 crvl0 xxxxxxxx 23 22 21 20 19 18 17 16 crvl23 crvl22 crvl21 crvl20 crvl19 crvl18 crvl17 crvl16 xxxxxxxx 17348b-16 ctcreg C bits 23:0 C crvl 23:0 C current value 23:0 this is a three-byte register which decrements to keep track of the number of bytes transferred during a dma transfer. reading these registers returns the current value of the counter. the counter will decrement by one for every byte and by two for every word transferred. the transaction is complete when the count reaches zero, and bit 4 of the status register (04h) is set. should the sequence terminate early, the sum of the values in the current fifo (07h) and the current transfer count register reflect the number of bytes remaining. the least significant byte is located at address 00h, the middle byte is located at address 01h, and the most sig- nificant byte is located at address 0eh. register 0eh extends the total width of the register from 16 to 24 bits, and is only enabled when the enable features bit (bit 6) of control register two is set to a value of `1'. these registers are automatically loaded with the val- ues in the start transfer count register every time a dma command is issued. however, following a chip or power on reset, up until the time register 0eh is loaded, the am53cf94/96s part-unique id can be obtained by reading register 0eh. in the target mode, this counter is decremented by the active edge of dack during the data-in phase and by reqc during the data-out phase. in the initiator mode, the counter is decremented by the active edge of dack during the synchronous data-in phase or by ackc during the asynchronous data-in phase and by dack during the data-out phase. start transfer count register (00h, 01h, 0eh) write only start transfer count register stcreg address: 00 hC 01 h type: write 15 14 13 12 11 10 9 8 stvl15 stvl14 stvl13 stvl12 stvl11 stvl10 stvl9 stvl8 xxxxxxxx 76543210 stvl7 stvl6 stvl5 stvl4 stvl3 stvl2 stvl1 stvl0 xxxxxxxx 23 22 21 20 19 18 17 16 stvl23 stvl22 stvl21 stvl20 stvl19 stvl18 stvl17 stvl16 xxxxxxxx 17348b-17 stcreg C bits 15:0 C stvl 15:0 C start value 15:0 this is a three-byte register which contains the number of bytes to be transferred during a dma operation. the value in the start transfer count register must be pro- grammed prior to command execution. the least significant byte is located at address 00h, the middle byte is located at address 01h, and the most sig- nificant byte is located at address 0eh. register 0eh extends the total width of the register from 16 to 24 bits, and is only enabled when the enable features bit (bit 6) of control register two is set to a value of 1. this sets the maximum transfer count to 16.78 mbytes. when a value of 0 is written to these registers, the transfer count will be set to the maximum. a dma nop com- mand must be issued before the transfer counter values can be written to 00h, 01h, and 0eh. these registers retain their value until overwritten, and are therefore unaffected by a hardware or software re- set. this reduces programming redundancy since it is no longer necessary to reprogram the count for subse- quent dma transfers of the same size.
p r e l i m i n a r y amd 18 am53cf94/am53cf96 fifo register (02h) read/write fifo register ffreg address: 02 h type: read/write 76543210 ff7 ff6 ff5 ff4 ff3 ff2 ff1 ff0 00000000 17348b-18 ffreg C bits 7:0 C ff 7:0 C fifo 7:0 the fifo on the am53cf94/96 is 16 bytes deep and is used to transfer scsi data to and from the esc. the bottom of the fifo may be accessed via a read or write to this register. this is the only register that can also be accessed by dack along with dmard or dmawr or with req or ack . this register is reset to zero by hard- ware or software reset, or at the start of a selection or reselection sequence, or if clear fifo command is issued. command register (03h) read/write command register cmdreg address: 03 h type: read/write 76543210 dma cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 xxxxxxxx command 6:0 direct memory access 17348b-19 commands to the esc are issued by writing to this reg- ister which is two bytes deep. commands may be queued, and will be read from the bottom of the queue. at the completion of the bottom command, the top com- mand, if present, will drop to the bottom of the register to begin execution. all commands are executed within six clock cycles of dropping to the bottom of the command register, with the exception of the reset scsi bus, re- set device, and dma stop commands. these com- mands are not queued and are executed within four clock cycles of being loaded into the top this register. interrupts are sometimes generated upon command completion. should both commands generate inter- rupts, and the first interrupt has not been serviced, the interrupt from the second (top) command will be stacked behind the first. the status register, interrupt register, and internal state register will be updated to apply to the second interrupt after the microprocessor services the first interrupt. reading this register will return the command currently being executed (or the last command executed if there are no pending commands). when this register is cleared, existing commands will be terminated and any queued commands will be ignored. however, it does not reset the register bits to 00h. cmdreg C bit 7 C dma C direct memory access when set, this bit notifies the device that the command is a dma instruction, when reset it is a non-dma instruc- tion. for dma instructions the current transfer count register (ctcreg) will be loaded with the contents of the start transfer count register (stcreg). the data is then transferred and the ctcreg is decremented for each byte until it reaches zero. cmdreg C bits 6:0 C cmd 6:0 C command 6:0 these command bits decode the commands that the device needs to perform. there are a total of 31 com- mands grouped into four categories. the groups are initiator commands, target commands, selection/ reselection commands and general purpose com- mands.
p r e l i m i n a r y amd 19 am53cf94/am53cf96 initiator commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 0010000 information transfer 00100 01 initiator command complete steps 0010010 message accepted 0011000 transfer pad bytes 0011010 *set atn 0011011 *reset atn cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 0100000 send message 0100001 send status 0100010 send data 0100011 disconnect steps 0100100 terminate steps 0100101 target command complete steps 0100111 *disconnect 0101000 receive message steps 0101001 receive command 0101010 receive data 0101011 receive command steps 0000100 *dma stop 0000101 access fifo command idle commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 1000000 reselect steps 10000 01 select without atn steps 1000010 select with atn steps 1000011 select with atn and stop steps 1000100 *enable selection/reselection 1000101 disable selection/reselection 1000110 select with atn3 steps 1000111 reselect with atn3 steps general commands cmd6 cmd5 cmd4 cmd3 cmd2 cmd1 cmd0 command 0000000 *no operation 00000 01 *clear fifo 0000010 *reset device 0000011 reset scsi bus target commands note: *denotes commands which do not generate interrupts upon completion.
p r e l i m i n a r y amd 20 am53cf94/am53cf96 status register (04h) read status register statreg address: 04 h type: read 76543210 int ioe pe ctz gcv msg c/d i/o 0000 0 xxx illegal operation error parity error count to zero group code valid message command/data input/output interrupt 17348b-20 this read only register contains flags to indicate the status and phase of the scsi transactions. it indicates whether an interrupt or error condition exists. it should be read every time the host is interrupted to determine which device is asserting an interrupt. if the enf bit is set (cntlreg2, bit 6), the scsi bus phase of the last complete command (preceding the interrupt) will be latched until the interrupt status register (instreg) is read. if the enf bit is disabled, this register will reflect the current bus phase. if command stacking is used, two interrupts might occur. reading this register will clear the status information for the first interrupt and update the status register for the second interrupt. statreg C bit 7 C int C interrupt the int bit is set when the device asserts the interrupt output. this bit will be cleared by a hardware or software reset. reading the interrupt status register (instreg) will deassert the interrupt output and also clear this bit. statreg C bit 6 C ioe C illegal operation error the ioe bit is set when an illegal operation is attempted. this condition will not cause an interrupt, it will be de- tected by reading the status register (statreg) while servicing another interrupt. the following conditions will cause the ioe bit to be set: n dma and scsi transfer directions are opposite. n fifo overflows or data is overwritten. n in initiator mode an unexpected phase change detected during synchronous data transfer. n command register overwritten. this bit will be cleared by reading the interrupt status register (instreg) or by a hard or soft reset. statreg C bit 5 C pe C parity error the pe bit is set if any of the parity checking options are enabled and the device detects a parity error on bytes sent or received on the scsi bus. parity options are controlled by bits 5:4 in control register one (cntlreg1), and by bits 2:0 in control register two (cntlreg2). the combination of enabled options will determine if parity is generated from the data bytes internally by the chip, or if it is passed between buffer and scsi bus without being altered. detection of a parity error condition will not cause an interrupt but will be reported with other interrupt causing conditions. this bit will be cleared by reading the interrupt status register (instreg) or by a hard or soft reset. statreg C bit 4 C ctz C count to zero the ctz bit is set when the current transfer count register (ctcreg) has counted down to zero. this bit will be reset when the ctcreg is written with a non- zero value. reading the interrupt status register (instreg) will not affect this bit. this bit will however be cleared by a hard or soft reset. note: a non-dma nop will not reset the ctz bit since it does not load the ctcreg. however, a dma nop will reset this bit since it loads the ctcreg. statreg C bit 3 C gcv C group code valid the gcv bit is set if the group code field in the com- mand descriptor block (cdb) is one that is defined by the ansi committee in their document x3.131 C 1986. if the scsi-2 feature enable (s2fe) bit in the control register 2 (cntlreg2) is set, group 2 commands will be treated as ten byte commands and the gcv bit will be set. if s2fe is reset then group 2 commands will be treated as reserved commands. group 3 and 4 com- mands will always be considered reserved commands. the device will treat all reserved commands as six byte commands. group 6 commands will always be treated as vendor unique six byte commands and group 7 com- mands will always be treated as vendor unique ten byte commands. the gcv bit is cleared by reading the interrupt status register (instreg) or by a hard or soft reset.
p r e l i m i n a r y amd 21 am53cf94/am53cf96 statreg C bit 2 C msg C message statreg C bit 1 C c/d C command/data statreg C bit 0 C i/o C input/output bit2 bit1 bit0 msg c/d i/o scsi phase 1 1 1 message in 1 1 0 message out 1 0 1 reserved 1 0 0 reserved 0 1 1 status 0 1 0 command 0 0 1 data_in 0 0 0 data_out the msg, c/d and i/o bits together can be referred to as the scsi phase bits. they indicate the phase of the scsi bus. these bits may be latched or unlatched depending on whether or not the enf bit in control register two is set. in the latched mode the scsi phase bits are latched at the end of a command and the latch is opened when the interrupt status register (instreg) is read. in the un- latched mode, they indicate the phase of the scsi bus when this register is read. scsi destination id register (04h) write res res res res res 00000 scsi destination id register sdidreg address: 04 h type: write 76543210 did2 did1 did0 xxx reserved reserved reserved reserved scsi destination id 2:0 reserved 17348b-21 sdidreg C bits 7:3 C res C reserved sdidreg C bits 2:0 C did 2:0 C destination id 2:0 the did 2:0 bits are the encoded scsi id of the device on the scsi bus which needs to be selected or reselected. at power-up the state of these bits is undefined. the did 2:0 bits are not affected by reset. did2 did1 did0 scsi id 1117 1106 1015 1004 0113 0102 0011 0000
p r e l i m i n a r y amd 22 am53cf94/am53cf96 interrupt status register (05h) read srst icmd dis sr so 00000 interrupt status register instreg address: 05h type: read 76543210 resel sela sel 000 invalid command disconnected service request successful operation selected with attention scsi reset selected reselected 17348b-22 the interrupt status register (instreg) will indicate the reason for the interrupt. this register is used with the status register (statreg) and internal state register (isreg) to determine the reason for the interrupt. reading the instreg will clear all three registers. therefore the status register (statreg) and internal state register (isreg) should be examined prior to reading the instreg. instreg C bit 7 C srst C scsi reset the srst bit will be set if a scsi reset is detected and scsi reset reporting is enabled via the disr (bit 6) of control register one (cntlreg1). instreg C bit 6 C icmd C invalid command the icmd bit will be set if the device detects an illegal command code. this bit is also set if a command code is detected from a mode that is different from the mode the device is currently in. once this bit is set, and invalid command interrupt will be generated. instreg C bit 5 C dis C disconnected the dis bit can be set in the target or the initiator mode when the device disconnects from the scsi bus. in the target mode this bit will be set if a terminate or a com- mand complete steps causes the device to disconnect from the scsi bus. in the initiator mode this bit will be set if the target disconnects; while in idle mode, this bit will be set if a selection or reselection timeout occurs. instreg C bit 4 C sr C service request the sr bit can be set in the target or the initiator mode when another device on the scsi bus has a service request. in the target mode this bit will be set when the initiator asserts the atn signal. in the initiator mode this bit is set when a command steps successfully com- pleted command is issued. instreg C bit 3 C so C successful operation the so bit can be set in the target or the initiator mode when an operation has successfully completed. in the target mode this bit will be set when any target or idle state command is completed. in the initiator mode this bit is set after a target has been successfully selected, after a command has successfully completed and after an information transfer command when the target requests a message in phase. instreg C bit 2 C resel C reselected the resel bit is set at the end of the reselection phase indicating that the device has been reselected as an initiator. instreg C bit 1 C sela C selected with attention the sela bit is set at the end of the selection phase indi- cating that the device has been selected as a target by the initiator and that the atn signal was active during the selection. instreg C bit 0 C sel C selected the sel bit is set at the end of the selection phase indi- cating that the device has been selected as a target by the initiator and that the atn signal was inactive during the selection.
p r e l i m i n a r y amd 23 am53cf94/am53cf96 scsi timeout register (05h) write scsi timeout register stimreg address: 05 h type: write 76543210 stim7 stim6 stim5 stim4 stim3 stim2 stim1 stim0 xxxxxxxx 17348b-23 this register determines how long the initiator (target) will wait for a response to a selection (reselection) before timing out. it should be set to yield 250 ms to comply with ansi standards for scsi, but the maximum time out period may be calculated using the following formulas. note: a hardware reset will clear this register. stimreg C bits 7:0 C stim 7:0 C scsi timer 7:0 the value loaded in stim 7:0 can be calculated as shown below: stim 7:0 = [(scsi time out) (clock frequency) / (8192 (clock factor))] example: scsi time out (in seconds): 250 ms. (recommended by the ansi standard) = 250 x 10 C3 s. clock frequency: 20 mhz. (assume) = 20 x 10 6 hz. clock factor: clkf 2:0 from clock conversion register (09h) = 5 stim 7:0 = (250 x 10 C3 ) x (20 x 10 6 ) / (8192 (5)) = 122 decimal internal state register (06h) read internal state register isreg address: 06 h type: read 76543210 res res res res sof is2 is1 is0 xxxx 0 000 reserved reserved reserved synchronous offset flag internal state 2:0 reserved 17348b-24 the internal state register (isreg) tracks the progress of a sequence-type command. it is updated after each successful completion of an intermediate operation. if an error occurs, the host can read this register to determine the point where the command failed and take the necessary procedure for recovery. reading the interrupt status register (instreg) while an interrupt is pending will clear this register. a hard or soft reset will also zero this register . isreg C bits 7:4 C res C reserved isreg C bit 3 C sof C synchronous offset flag the sof is reset when the synchronous offset register (sofreg) has reached its maximum value. note: the sof bit is active low. isreg C bits 2:0 C is 2:0 C internal state 2:0 the is 2:0 bits along with the interrupt status register (instreg) indicates the status of the successfully completed intermediate operation. refer to the status decode section for more details.
p r e l i m i n a r y amd 24 am53cf94/am53cf96 initiator select without atn steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed. selection time-out occurred, then disconnected 4 18 selection without atn steps fully executed 3 18 sequence halted during command transfer due to premature phase change (target) 2 18 arbitration and selection completed; sequence halted because target failed to assert command phase initiator select with atn steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed. selection time-out occurred then disconnected 4 18 selection with atn steps fully executed 3 18 sequence halted during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo flags 2 18 message out completed; sent one message byte with atn true, then released atn ; sequence halted because target failed to assert command phase after message byte was sent 0 18 arbitration and selection completed; sequence halted because target did not assert message out phase; atn still driven by esc initiator select with atn3 steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed. selection time-out occurred then disconnected 4 18 selection with atn3 steps fully executed 3 18 sequence halted during command transfer due to premature phase change; some cdb bytes may not have been sent; check fifo flags 2 18 one, two, or three message bytes sent; sequence halted because target failed to assert command phase after third message byte, or prematurely released message out phase; atn released only if third message byte was sent 0 18 arbitration and selection completed; sequence halted because target failed to assert message out phase; atn still driven by esc initiator select with atn and stop steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 0 20 arbitration steps completed. selection time-out occurred then disconnected 0 18 arbitration and selection completed; sequence halted because target failed to assert message out phase; atn still asserted by esc 1 18 message out completed; one message byte sent; atn on
p r e l i m i n a r y amd 25 am53cf94/am53cf96 target select without atn steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 11 selected; received entire cdb; check group code valid bit 1 11 sequence halted in command phase due to parity error; some cdb bytes may not have been received; check fifo flags; initiator asserted atn in command phase 2 01 selected; received entire cdb; check group code valid bit 1 01 sequence halted in command phase because of parity error; some cdb bytes may not have been received; check fifo flags 0 01 selected; loaded bus id into fifo; null-byte message loaded into fifo target select with atn steps, scsi-2 bit not set internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 12 selection complete; received one message byte and entire cdb; initiator as- serted atn during command phase 1 12 halted in command phase; parity error and atn true 0 12 selected with atn ; stored bus id and one message byte; sequence halted be- cause atn remained true after first message byte 2 02 selection completed; received one message byte and the entire cdb 1 02 sequence halted in command phase because of parity error; some cdb bytes not received; check group code valid bit and fifo flags 0 02 selected with atn ; stored bus id and one message byte; sequence halted be- cause of parity error or invalid id message target select with atn steps, scsi-2 bit set internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 6 12 selection completed; received three message bytes and entire cdb. atn is true 5 12 halted in command phase; parity error and atn true 412 atn remained true after third message byte 2 12 selection completed; initiator deasserts atn after receipt of one message byte; entire cdb received. atn asserted during command phase 1 12 sequence halted during command phase because of parity error; one message byte received; some bytes of cdb not received; parity error and atn true 0 12 selected with atn ; stored bus id and one message byte; sequence halted be- cause of parity error or invalid id message; atn is true 6 02 selection completed; received three message bytes and the entire cdb 5 02 received three message bytes then halted in command phase because of parity error; some cdb bytes not received; check group code valid bit and fifo flags 4 02 parity error during second or third message byte 2 02 selection completed; initiator deasserts atn after receipt of one message byte; entire cdb received 1 02 sequence halted during command phase because of parity error; one message byte received; some bytes of cdb not received; check fifo flags and group code valid bit 0 02 selected with atn ; stored bus id and one message byte; sequence halted be- cause of parity error or invalid id message
p r e l i m i n a r y amd 26 am53cf94/am53cf96 target receive command steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 18 received entire cdb; initiator asserted atn 1 18 sequence halted during command transfer due to parity error; atn asserted by initiator 2 08 received entire cdb 1 08 sequence halted during command transfer due to parity error; check fifo flags target disconnect steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 28 disconnect steps fully executed; disconnected; bus is free 1 18 two message bytes sent; sequence halted because initiator asserted atn 0 18 one message byte sent; sequence halted because initiator asserted atn target terminate steps internal state interrupt status register (06h) register (05h) explanation bits 2:0 (hex) bits 7:0 (hex) 2 28 terminate steps fully executed; disconnected; bus is free 1 18 status and message bytes sent; sequence halted because initiator asserted atn 0 18 status byte sent; sequence halted because initiator asserted atn
p r e l i m i n a r y amd 27 am53cf94/am53cf96 synchronous transfer period register (06h) write 6 synchronous transfer period register stpreg address: 06 h type: write 7 543210 res res res stp4 stp3 stp2 stp1 stp0 xxx0 0 101 reserved reserved synchronous transfer period 4:0 reserved 17348b-25 the synchronous transfer period register (stpreg) contains a 5-bit value indicating the number of clock cy- cles each byte will take to be transferred over the scsi bus in synchronous mode. the minimum value allowed is 4. the stpreg defaults to 5 clocks/byte after a hard or soft reset. stpreg C bits 7:5 C res C reserved stpreg C bits 4:0 C stp 4:0 C synchronous transfer period 4:0 the stp 4:0 bits are programmed to specify the syn- chronous transfer period or the number of clock cycles for each byte transfer in the synchronous mode. the minimum value for stp 4:0 is 4 clocks/byte. missing table entries follow the binary code. clocks/ stp4 stp3 stp2 stp1 stp0 byte 0 01004 0010 15 0 01106 0 01117 1 111131 0 000032 0 000133 0 001034 0 001135
p r e l i m i n a r y amd 28 am53cf94/am53cf96 current fifo/internal state register (07h) read current fifo/internal state register cfisreg address: 07 h type: read 76543210 is2 is1 is0 cf4 cf3 cf2 cf1 cf0 0000 0 000 internal state 2:0 current fifo 4:0 17348b-26 this register has two fields, the current fifo field and the internal state field. cfisreg C bits 7:5 C is 2:0 C internal state 2:0 the internal state register (isreg) tracks the progress of a sequence-type command. the is 2:0 bits are duplicated from the is 2:0 field in the internal state register (isreg) in the normal mode. if the device is in the test mode, (see cntlreg1, bit 3) is 0 is set to indicate that the offset value is non-zero. a non-zero value indicates that synchronous data transfer can continue. a zero value indicates that the synchronous offset count has been reached and no more data can be transferred until an acknowledge is received. cfisreg C bits 4:0 C cf 4:0 C current fifo 4:0 the cf 4:0 bits are the binary coded value of the num- ber of bytes in the fifo. these bits should not be read when the device is transferring data since this count may not be stable. synchronous offset register (07h) write synchronous offset register sofreg address: 07 h type: write 76543210 so3 so2 so1 so0 rad1 rad0 raa1 raa0 0000 0 000 req / ack assertion 1:0 synchronous offset 3:0 req / ack deassertion 1:0 17348b-27 the synchronous offset register (sofreg) controls req / ack deassertion/assertion delay and stores a 4-bit count of the number of bytes that can be sent to (or received from) the scsi bus during synchronous transfers without an ack (or req ). bytes exceeding the threshold will be sent one byte at a time (asynchronously). that is, each byte will require an ack / req handshake. to set up an asynchronous transfer, the sofreg is set to zero. the sofreg is set to zero after a hard or soft reset. sofreg C bits 7:6 C rad 1:0 these bits may be programmed to control the deasser- tion delay of the req and ack signals during synchro- nous transfers. deassertion delay is expressed as input clock cycles, and depends on the implementation of fastclk. (see cntlreg3, bit 3)
p r e l i m i n a r y amd 29 am53cf94/am53cf96 deassertion delay sofreg fastclk req/ack bits 7:6 ctrl 3, bit 3 input clk cycles 00 0 default C 0 cycles 01 0 1/2 cycle early 10 0 1 cycle delay 11 0 1/2 cycle delay 00 1 default C 0 cycles 01 1 1/2 cycle delay 10 1 1 cycle delay 11 1 1 1/2 cycles delay sofreg C bits 5:4 C raa 1:0 these bits may be programmed to control the assertion delay of the req and ack signals during synchronous transfers. unlike deassertion delay, assertion delay is independent of the fastclk setting. assertion delay sofreg req/ack bits 5:4 input clk cycles 00 default C 0 cycles 01 1/2 cycle delay 10 1 cycle delay 11 1 1/2 cycles delay sofreg C bits 3:0 C so 3:0 C synchronous offset 3:0 the so 3:0 bits are the binary coded value of the num- ber of bytes that can be sent to (or received from) the scsi bus without an ack (or req ) signal. a zero value designates asynchronous xfer , while a non-zero value designates the number of bytes for synchronous transfer. control register one (08h) read/write control register one cntlreg1 address: 08 h type: read/write 76543210 etm disr pte pere ste cid2 cid1 cid0 0000 0 xxx disable interrupt on scsi reset parity test enable parity error reporting enable self test enable chip id 2:0 extended timing mode 17348b-28 the control register 1 (cntlreg1) sets up the device with various operating parameters. cntlreg1 C bit 7 C etm C extended timing mode enabling this feature will increase the minimum setup time for data being transmitted on the scsi bus. this bit should only be set if the external cabling conditions pro- duce scsi timing violations. fastclk operation is unaffected by this feature. cntlreg1 C bit 6 C disr C disable interrupt on scsi reset the disr bit masks the reporting of the scsi reset. when the disr bit is set and a scsi reset is asserted, the device will disconnect from the scsi bus and remain idle without interrupting the host processor. when the disr bit is reset and a scsi reset is asserted the device will respond by interrupting the host processor. the disr bit is reset to zero by a hard or soft reset. cntlreg1 C bit 5 C pte C parity test enable the pte bit is for test use only. when the pte bit is set the parity on the output (scsi or host processor) bus is forced to the value of the msb (bit 7) of the output data from the internal fifo. this allows parity errors to be created to test the hardware and software. the pte bit is reset to zero by a hard or soft reset. this bit should not be set in normal operation. cntlreg1 C bit 4 C pere C parity error report- ing enable the pere bit enables the checking and reporting of par- ity errors on incoming scsi bytes during the information transfer phase. when the pere bit set and bad parity is detected, the pe bit in the statreg is will be set but an interrupt will not be generated. in the initiator mode the atn signal will also be asserted on the scsi bus. when
p r e l i m i n a r y amd 30 am53cf94/am53cf96 the pere bit is reset and bad parity occurs it is not de- tected and no action is taken. cntlreg1 C bit 3 C ste C self test enable the ste bit is for test use only. when the ste bit is set the device is placed in a test mode which enables the device to access the test register at address 0ah. to re- set this bit and to resume normal operation the device must be issued a hard or soft reset. cntlreg1 C bit 2:0 C cid 2:0 C chip id 2:0 the chip id 2:0 bits specify the binary coded value of the device id on the scsi bus. the device will arbitrate with this id and will respond to selection or reselection to this id. at power-up the state of these bit are unde- fined. these bits are not affected by hard or soft reset. clock factor register (09h) write 3 clock factor register clkfreg address: 09 h type: write 7654 210 res res res res res clkf2 clkf1 clkf0 xxxxx010 reserved reserved reserved reserved clock factor 2:0 reserved 17348b-29 the clock factor register (clkfreg) must be set to indicate the input frequency range of the device. this value is crucial for controlling various timings to meet the scsi specification. the value of bits clkf 2:0 can be calculated by rounding off the quotient of (input clock frequency in mhz)/(5 mhz). the device has a fre- quency range of 10 to 40 mhz. clkfreg C bits 7:3 C res C reserved clkfreg C bits 2:0 C clkf 2:0 C clock factor 2:0 the clkf 2:0 bits specify the binary coded value of the clock factor. the clkf 2:0 bits will default to a value of 2 by a hard or soft reset. input clock clkf2 clkf1 clkf0 frequency in mhz 01 0 10 0 1 1 10.01 to 15 1 0 0 15.01 to 20 1 0 1 20.01 to 25 1 1 0 25.01 to 30 1 1 1 30.01 to 35 0 0 0 35.01 to 40
p r e l i m i n a r y amd 31 am53cf94/am53cf96 forced test mode register (0ah) write 3 forced test mode register ftmreg address: 0a h type: write 7654 210 res res res res res fhi fim ftm xxxxx000 reserved reserved reserved reserved forced high impedance mode forced initiator mode forced target mode reserved 17348b-30 the forced test mode register (ftmreg) is for test use only. the ste bit in the control register one (cntlreg1) must be set for the ftmreg to operate. ftmreg C bits 7:3 C res C reserved ftmreg C bit 2 C fhi C forced high impedance mode the fhi bit when set places all the output and bidirec- tional pins into a high impedance state. it is zeroed by a hardware or chip reset. ftmreg C bit 1 C fim C forced initiator mode the fim bit when set forces the esc into the initiator mode. as an initiator, the device will drive scsi data lines, and ack or atn (depending on the bus phase and the command loaded in the command register). the esc will remain in this mode for as long as bsy is as- serted, or until a reset scsi bus or reset device com- mand occurs. during normal operation this bit must not be set. ftmreg C bit 0 C ftm C forced target mode the ftm bit when set forces the esc into the target mode. as a target, the device does not assert bsy ; rather, it drives scsi data lines, req , msg , c/d or i/o (depending on the command loaded in the command register). the esc will remain in this mode until a dis- connect steps, reset scsi bus, or reset device com- mand occurs. during normal operation this bit must not be set. control register two (0bh) read/write data alignment enable control register two cntlreg2 address: 0b h type: read/write 76543210 dae enf sbo tsdr s2fe acdpe pgrp pgdp 0000 0 000 enable features select byte order tri-state dma request scsi-2 features enable abort on command/data parity error pass through/generate register parity pass through/generate data parity 17348b-31 the control register two (cntlreg2) sets up the de- vice with various operating parameters. cntlreg2 C bit 7 C dae C data alignment enable the dae bit is used in the initiator synchronous data-in phase only. when the dae bit is set one byte is reserved at the bottom of the fifo when the phase changes to the synchronous data-in phase. the contents of this byte will become the lower byte of the dma word (16-bit) transferred to the memory, the upper byte being the first byte of the first word received from the scsi bus. note: if an interrupt is received for a misaligned boundary on a phase change to synchronous data the following recov- ery procedure may be followed. the host processor should copy the byte at the start address in the host memory to the data alignment register 0fh (dalreg)
p r e l i m i n a r y amd 32 am53cf94/am53cf96 and then issue an information transfer command. the first word the device will write to the memory (via dma) will consists of the lower byte from the dalreg and the upper byte from the first byte received from the scsi bus. the dae bit must be set before the phase changes to the synchronous data-in. the dae bit is reset to zero by a hard or soft reset or by writing the dalreg when in- terrupted in the synchronous data-in phase. cntlreg2 C bit 6 C enf C enable features a software or hardware reset will clear this bit to its de- fault value of 0; a scsi reset will leave this bit unaf- fected. when set to a value of 1, this bit activates the following product enhancements: 1) the current transfer count register high (0eh) will be enabled, extending the transfer counter from 16 to 24 bits to allow for larger transfers. 2) following a chip or power on reset, up until the point where the current transfer count register high (0eh) is loaded with a value, it is possible to read the part-unique id from this register. 3) the scsi phase will be latched at the completion of each command by bits 2:0 in the status register (statreg). when this bit is 0, the status register (statreg) will reflect real-time scsi phases. 4) the enable signal for the differential drivers may be delayed to avoid bus contention on the scsi differential lines when the direction for i/o is switching. when the scsi bus changes direction from input to output, the output drivers are not asserted for two clock cycles to avoid bus contention. when the bus changes from output to input, sdc 7:0 are given time to switch direction before the scsi drivers are asserted. cntlreg2 C bit 5 C sbo C select byte order the sbo bit is used only when the busmd 1:0 = 10 to enable or disable the byte control on the dma interface. when sbo is set and the busmd 1:0 = 10, the byte con- trol inputs bhe and as0 control the byte positions. when sbo is reset the byte control inputs bhe and as0 are ignored. cntlreg2 C bit 4 C tsdr C tri-state dma request the tsdr bit when set sends the dreq output signal to high impedance state and the device ignores all activity on the dma request (dreq) input. this is useful for wiring-or several devices that share a common dma request line. when the tsdr bit is reset the dreq output is driven to ttl levels. cntlreg2 C bit 3 C s2fe C scsi-2 features enable the s2fe bit allows the device to recognize two scsi-2 features: the extended message feature and the group 2 command recognition. (these features can also be controlled independently by bits 6:5 in cntlreg3). extended message feature: when the s2fe bit is set and the device is selected with attention, the device will monitor the atn signal at the end of the first message byte. if the atn signal is active, the device will request two more message bytes before switching to the com- mand phase. if the atn signal is inactive the device will switch to the command phase. when the s2fe bit is re- set as a target the device will request a single message byte. as an initiator, the device will abort the selection sequence if the target does not switch to the command phase after receiving a single message byte. group 2 command recognition: when the s2fe bit is set, the gcv (group code valid) bit in the statreg (04h) is set, allowing the group 2 commands to be rec- ognized as 10 byte commands. when the s2fe bit is reset, the gcv bit in the statreg is not set, and the device will interpret the group 2 commands as reserved commands and will request 6 byte commands. cntlreg2 C bit 2 C acdpe C abort on command/ data parity error the acdpe bit when set allows the device to abort a command or data transfer when a parity error is de- tected. when the acdpe bit is reset parity error is ig- nored. cntlreg2 C bit 1 C pgrp C pass through/gener- ate register parity the pgrp bit, when set, allows parity from dmap1C0 to pass during register writes to the fifo. enabling this bit also causes parity checking as data is unloaded from the fifo to the scsi bus. when this bit is reset to zero, parity is generated for reg- ister writes to the fifo, however no additional checking will be done as fifo data is unloaded to the scsi bus unless the pgdp bit is set. cntlreg2 C bit 0 C pgdp C pass through/gener- ate data parity the pgdp bit, when set, allows parity from dmap1C0 to pass during dma writes to the fifo. parity checking will also be performed as data is unloaded from the fifo to the scsi bus. when this bit is reset to zero, parity is generated during dma writes to the fifo, however no additional check- ing will be done as fifo data is unloaded, unless the pgrp bit is set.
p r e l i m i n a r y amd 33 am53cf94/am53cf96 4 control register three cntlreg3 address: 0c h type: read/write 765 3210 adid chk qtag g2cb fast scsi fast clk lbtm mdm bs8 00000000 qtag control group 2 command block fastscsi fastclk last byte transfer mode modify dma mode burst size 8 additional id check control register three (0ch) read/write 17348b-32 cntlreg3 C bit 7 C adidchk C additional id check enables additional check on id message during bus- initiated select or reselect with atn . the esc will check bits 7, and bits 5:3 in the first byte of the id mes- sage during selection of reselection. an interrupt will be generated if bit 7 is 0, or if bits 5, 4, or 3 are 1. cntlreg3 C bit 6 C qtag C qtag control this bit controls the queue tag feature in the esc. when enabled, the esc is capable of receiving 3-byte messages during bus-initiated select/reselect with atn . (bit 3, control register two also enables this fea- ture). the 3-byte message consists of one byte identify message and two bytes of queue tag message. the esc will check the second byte for values of 20h, 21h, and 22h. if this condition is not satisfied, the sequence halts and the esc generates an interrupt. when the qtag feature is not enabled, the esc halts the selected with atn sequence following the receipt of one id message byte if atn is still true. cntlreg3 C bit 5 C g2cb C group 2 command block when this bit is set, the esc is capable of recognizing 10-byte group 2 commands as valid cdbs (command descriptor blocks). (this feature is also controlled by bit 3 of cntlreg2). when this feature is enabled, the target receives 10 bytes of group 2 commands, and sets the group code valid bit (bit 3) in status register (statreg). when this feature is disabled, the target receives only 6 bytes of command code, and does not set bit 3 in register (04h). this bit may be programmed in conjunction with bit 6 (described above) to send 1 or 3 byte messages with 6 or 10 byte cdbs. the following table illustrates the transmission options: cntlreg3 C bit 4 C fastscsi C fast scsi cntlreg3 C bit 3 C fastclk C fast scsi clocking these bits configure the escs state machine to support both fast scsi timings and scsi-1 timings. these bits will affect the scsi transfer rate, and must be consid- ered in conjunction with the escs clock frequency and mode of operation. cntlreg3 cntlreg3 cntlreg2 bit 6 bit 5 bit 3 enabled qtag g2cb s2fe features CC CC 1 10-byte cdb, 3-byte message 1 0 0 3-byte message 0 1 0 10-byte cdb 1 1 0 10-byte cdb, 3-byte message 0 0 0 features disabled CC = dont care
p r e l i m i n a r y amd 34 am53cf94/am53cf96 cntlreg3 cntlreg3 fastscsi fastclk clock mode of bit 4 bit 3 frequency operation 1 1 25C40 mhz 10 mbytes/ sec, fast scsi 0 1 25C40 mhz 5 mbytes/sec, scsi-1 CC 0 < = 25 mhz 5 mbytes/sec, scsi-1 CC = dont care cntlreg3 C bit 2 C lbtm C last byte transfer mode the lbtm bit specifies how the last byte in an odd byte transfer is handled during 16-bit dma transfers (modes 1, 2, 3). this mode is not used if byte control is selected via busmd 1:0 = 10 and sbo (select byte order) bit in the cntlreg2is set to 1. this mode has no affect dur- ing 8-bit dma transfers (mode 0) and on transfers on the scsi bus. when the lbtm bit is set the dreq signal will not be asserted for the last byte, instead the host will read or write the last byte from or to the fifo. when the lbtm bit is reset the dreq signal will be asserted for the last byte and the following 16-bit dma transfer will contain the last byte on the lower bus. while the upper bus (dma 15:8/dmap 1) will be all ones. the lbtm bit is reset by hard or soft reset. cntlreg3 C bit 1 C mdm C modify dma mode the mdm bit is used to modify the timing of the dack signal with respect to the dmard and dmawr signals. the mdm bit is used in conjunction with the burst size 8 (bs8) bit in the cntlreg3. both bits have to be set for proper operation. when the mdm bit is set and the device is in a dma read or write mode the dack signal will remain asserted while the data is strobed by the dmard or dmawr sig- nals. in the dma read mode when busmd 1:0 = 11 the dack signal will toggle for every dma read. when the mdm bit is reset and the device is in a dma read or write mode the dack signal will toggle every time the data is strobed by the dmard or dmawr signals. cntlreg3 C bit 0 C bs8 C burst size 8 the bs8 bit is used to modify the timing of the dreq signal with respect to the dmard and dmawr signals. the bs8 bit is used in conjunction with the modify dma mode (mdm) bit in the cntlreg3. both bits have to be set for proper operation. when the bs8 bit is set the device delays the assertion of the dreq signal until 8 bytes or 4 words transfer is possible. when the bs8 bit is set and the device is in a dma write mode the dreq signal will be asserted only when 8 byte locations are available for writing. in the dma read mode the dreq signal will go active under the following circumstances: at the end of a transfer, n in the target mode, C when the transfer is complete or C when the atn signal is active n in the initiator mode, C when the current transfer register (ctcreg) is decremented to zero or C after any phase change in the middle of a transfer n in the initiator mode, C when the last 8 bytes of the fifo are full C during synchronous data-in transfer when the event transfer count register is greater than 7 and the last 8 bytes of the fifo are full. when the bs8 bit is reset and the device is in a dma read or write mode the dreq signal will toggle every time the data is strobed by the dmard or dmawr signals. using (bit 0 (bs8) and bit 1 (mdm) of control register three (cntlreg3), one can enable the differ- ent combination modes shown in the table below. maximum (mdm) (bs8) function synchronous bit 1 bit 0 offset 0 0 normal dma mode 15 0 1 burst size 8 mode 7 1 0 reserved C 1 1 modified dma mode 7
p r e l i m i n a r y amd 35 am53cf94/am53cf96 4 control register four cntlreg4 address: 00 h 765 3210 ge1 ge0 pwd res res (r) rae(w) rade res nu 000 0xx glitch eater power-down reserved res (r)/active negation ctl (w) active negation ctl. transfer count test enable control register four (0dh) 17348b-33 x0 this register is used to control several amd proprietary features implemented in the am53cf94/96. at power up, this register will show a 0 value on all bits except bit 4. cntlreg4 C bit 7:6 C ge1:0 C glitch eater the glitch eater circuitry has been implemented on all scsi input lines and are controlled by bits 7and 6. the valid signal window may be adjusted by setting the bits in the combinations listed below. cntlreg4 cntlreg4 bit 7 bit 6 single- ge1 ge0 ended differential 0 0 12 ns 0 ns 1 0 25 ns 25 ns 0 1 35 ns 35 ns 1 1 0 ns 12 ns cntlreg4 C bit 5 C pwd C power-down feature setting this bit to 1 will enable amds exclusive power- down feature. this will turn off the input buffers on all the scsi bus signal lines to reduce power consumption dur- ing the chips sleep mode. cntlreg4 C bit 4 C res this bit is reserved for internal use. cntlreg4 C bit 3 (read only) C res this bit is reserved for internal use. cntlreg4 C bit 3 (write only) C rae C active negation control cntlreg4 C bit 2 C rade C active negation control bits 2 and 3 control the active negation drivers which may be enabled on req , ack , or data lines. the fol- lowing table shows the programming options for this feature: cntlreg4 cntlreg4 bit 3 bit 2 function selected rae rade 0 0 active negation disabled 1 0 active negation on req and ack only CC 1 active negation on req , ack and data CC = dont care cntlreg4 C bit 1 C res this bit is reserved for internal use. cntlreg4 C bit 0 C nu C not used the ncr53cf94/96 uses this bit to control back-to- back transfers. this bit may be read or written but is not used by the am53cf94/96. back-to-back transfers are always enabled.
p r e l i m i n a r y amd 36 am53cf94/am53cf96 data alignment register (0fh) write 17348b34 da7 da6 da5 da4 da3 da2 da1 da0 00000000 data alignment register address: of h dalreg type: write 76543210 the data alignment register (dalreg) is used if the first byte of a 16bit dma transfer from the scsi bus to the host processor is misaligned. prior to issuing an in formation transfer command, the host processor must set the data alignment enable (dae) bit in control reg ister two (cntlreg2). this register may be loaded immediately following the phase change to synchronous data in. this byte will become the lsb of the first word transmitted from the fifo to the dma controller. the msb will be comprised of the first byte received over the scsi bus. together, these bytes constitute the first 16bit word transferred to memory. dalreg - bits 7:0 - da 7:0 - data alignment 7:0 partunique id register (0eh) read only this register extends the transfer counter from 16 to 24 bits and is only enabled when the enf bit is set (bit 6, control register two). the descriptions accompanying the start transfer count registers and the current count registers should be referenced for more informa tion regarding the transfer counter. this register is also used to store the partunique id code for the am53cf94/96. this information may be ac cessed when all of the following are true: 1) a value has not been loaded into this register 2) a dma nop command has been issued (code 80h) 3) bit 6 in control register two is set (enf bit) 4) a power up or chip reset has taken place when the above conditions are satisfied, the following bit descriptions apply: id am53cf94, 3 v 12 am53cf94, 5 v 12
p r e l i m i n a r y amd 37 am53cf94/am53cf96 commands the device commands can be broadly divided into two categories, dma commands and non-dma commands. dma commands are those which cause data movement between the host memory and the scsi bus while non- dma commands are those that cause data movement between the device fifo and the scsi bus. the msb of the command byte differentiate the dma from the non- dma commands. summary of commands non- dma dma mode mode initiator commands information transfer 10 90 initiator command complete steps 11 91 message accepted 12 C transfer pad bytes 18 98 set atn 1a C reset atn 1b C target commands send message 20 a0 send status 21 a1 send data 22 a2 disconnect steps 23 a3 terminate steps 24 a4 target command complete steps 25 a5 disconnect 27 a7 receive message 28 a8 receive command steps 29 a9 receive data 2a aa receive command steps 2b ab dma stop command 04 84 access fifo command 05 85 non- dma dma mode mode idle state commands reselect steps 40 c0 select without atn steps 41 c1 select with atn steps 42 c2 select with atn and stop steps 43 c3 enable selection/reselection 44 c4 disable selection/reselection 45 c5 select with atn3 steps 46 c6 reselect with atn3 steps 47 c7 general commands no operation 00 80 clear fifo 01 81 reset device 02 82 reset scsi bus 03 83 command code (hex.) command code (hex.) command command
p r e l i m i n a r y amd 38 am53cf94/am53cf96 command description initiator commands initiator commands are executed by the device when it is in the initiator mode. if the device is not in the initia- tor mode and an initiator command is received the device will ignore the command, generate an invalid command interrupt and clear the command register (cmdreg). should the target disconnect from the scsi bus by deasserting the bsy signal line while the esc (initiator) is waiting for the target to assert req , a disconnected interrupt will be issued 1.5 to 3.5 clock cycles following bsy going false. upon receipt of the last byte during msg in phase, ack will remain asserted to prevent the target from issuing any additional bytes, while the initiator decides to ac- cept/reject the message. if non-dma commands are used, the last byte signals the fifo is empty. if dma commands are used, the transfer counter signals the last byte. if parity checking is enabled in the initiator mode and an error is detected, atn will be asserted for the erroneous byte before deasserting ack . an exception to this is fol- lowing a phase change to synchronous data in. to program synchronous transfer, the synchronous offset register (sofreg) must be set to a non-zero value. while in this mode, if the phase changes to data in, the dma interface is disabled, and parity generation is delayed. the data in phase will latch the fifo flags to indicate the number of bytes in the fifo, clear the fifo, load the fifo with the first byte of data in, generate an interrupt, and continue to load the fifo with incoming bytes up to the synchronous offset. information transfer command (command code 10h/90h) the information transfer command is used to transfer information bytes over the scsi bus. this command may be issued during any scsi information transfer phase. synchronous data transmission requires use of the dma mode. the device will continue to transfer information until it is terminated by any one of the following conditions: n the target changes the scsi bus phase before the expected number of bytes are transferred. the device clears the command register (cmdreg), and generates a service interrupt when the target asserts req . n transfer is successfully complete. if the phase is message out, the device deasserts atn before asserting ack for the last byte of the message. when the target asserts req , a service interrupt is generated. n in the message in phase when the device receives the last byte. the device keeps the ack signal asserted and generates a successful operation interrupt. during synchronous data transfers the target may send up to the maximum synchronous threshold num- ber of req pulses to the initiator. if it is the synchronous data-in phase then the target sends the data and the req pulses. these bytes are stored by the initiator in the fifo as they are received. information transfer command, when issued during the following scsi phases and terminated in synchronous data phases, is handled as described below: n message in/status phase C when a phase change to synchronous data-in or synchronous data-out is detected by the device, the command register (cmdreg) is cleared and the dma interface is disabled to disallow any transfer of data phase bytes. if the phase change is to synchronous data-in and bad parity is detected on the data bytes coming in, it is not reported since the status register (statreg) will report the status of the command just completed. the parity error flag and the atn signal will be asserted when the transfer information command begins execution. n message out/command phase C when a phase change to synchronous data-in or synchronous data-out is detected by the device, the command register (cmdreg) is cleared and the dma interface is disabled to disallow any transfer of data phase bytes. if the phase change is to synchronous data-in and bad parity is detected on the data bytes coming in, it is not reported since the status register (statreg) will report the status of the command just completed. the parity error flag and the atn signal will be asserted when the transfer information command begins execution. the fifo register (ffreg) will be latched and will remain in that condition until the next command begins execution. the value in the ffreg indicates the number of bytes in the fifo when the phase changed to synchronous data-in. these bytes are cleared from the fifo, which now contains only the incoming data bytes. n in the synchronous data-out phase, the threshold counter is incremented as req pulses are received. the transfer is completed when the fifo is empty and the current transfer count register (ctcreg) is zero. the threshold counter will not be zero. n in the synchronous data-in phase, the current transfer count register (ctcreg) is decre- mented as bytes are read from the fifo rather than being decremented when the bytes are being written to the fifo. the transfer is completed when current transfer count register (ctcreg) is zero but the fifo may not be empty.
p r e l i m i n a r y amd 39 am53cf94/am53cf96 initiator command complete steps (command code 11h/91h) the initiator command complete steps command is normally issued when the scsi bus is in the status in phase. one status byte followed by one message byte is transferred if this command completes normally. after receiving the message byte the device will keep the ack signal asserted to allow the initiator to examine the message and assert the atn signal if it is unacceptable. the command terminates early if the target does not switch to the message in phase or if the target discon- nects from the scsi bus. message accepted command (command code 12h) the message accepted command is used to release the ack signal. this command is normally used to com- plete a message in handshake. upon execution of this command the device generates a service request inter- rupt after req is asserted by the target. after the device has received the last byte of message, it keeps the ack signal asserted. this allows the device to either accept or reject the message. to accept the message, message accepted command is issued. to reject the message the atn signal must be asserted (with the help of the set atn command) before issuing the message accepted command. in either case the message accepted command has to be issued to re- lease the ack signal. transfer pad bytes command (command code 18h/98h) the transfer pad bytes command is used to recover from an error condition. this command is similar to the information transfer command, only the information bytes consists of null data. it is used when the target ex- pects more data bytes than the initiator has to send. it is also used when the initiator receives more information than expected from the target. when sending data to the scsi bus, the fifo is loaded with null bytes which are sent out to the scsi bus. al- though an actual dma request is not made, dma must be enabled when pad bytes are transmitted since the esc uses current transfer count register (ctcreg) to terminate transmission. when receiving data from the scsi bus, the device will receive the pad bytes and place them on the top of the fifo and unload them from the bottom of the fifo. this command terminates under the same conditions as the information transfer command, but the device does not keep the ack signal asserted during the last byte of the message in phase. should this command terminate prematurely due to a disconnect or a phase change, (before the current transfer count register (ctcreg) decrements to zero), the fifo may contain residual pad bytes. set atn command (command code 1ah) the set atn command is used to drive the atn signal active on the scsi bus. an interrupt is not generated at the end of this command. the atn signal is deasserted before asserting the ack signal during the last byte of the message out phase. note: the atn signal is asserted by the device without this command in the following cases: n if any select with atn command is issued and the arbitration is won. n an initiator needs the targets attention to send a message. the atn signal is asserted before deasserting the ack signal. reset atn command (command code 1bh) the reset atn command is used to deassert the atn signal on the scsi bus. an interrupt is not generated at the end of this command. this command is used only when interfacing with devices that do not support the common command set (ccs). these older devices do not deassert their atn signal automatically on the last byte of the message out phase. this device does deas- sert its atn signal automatically on the last byte of the message out phase. target commands target commands are executed by the device when it is in the target mode. if the device is not in the target mode and a target command is received the device will ignore the command, generate an invalid command in- terrupt and clear the command register (cmdreg). a scsi bus reset during any target command will cause the device to abort the command sequence , flag a scsi bus reset interrupt (if the interrupt is enabled) and dis- connect from the scsi bus. normal or successful completion of a target command will cause a successful operation interrupt to be flagged. if the atn signal is asserted during a target command sequence the service request bit is asserted in the interrupt status register (instreg). if the atn signal is asserted when the device is in an idle state a service request interrupt will be generated, the suc- cessful operation bit in the interrupt status register (instreg) will be reset and the command register (cmdreg) cleared. send message command (command code 20h/a0h) the send message command is used by the target to inform the initiator to receive a message. the scsi bus phase lines are set to the message in phase and mes- sage bytes are transferred from the device fifo to the buffer memory. send status command (command code 21h/a1h) the send status command is used by the target to in- form the initiator to receive status information. the scsi bus phase lines are set to the status phase and status bytes are transferred from the target device to the initia- tor device.
p r e l i m i n a r y amd 40 am53cf94/am53cf96 send data command (command code 22h/a2h) the send data command is used by the target to inform the initiator to receive data bytes. the scsi bus phase lines are set to the data-in phase and data bytes are transferred from the target device to the initiator device. disconnect steps command (command code 23h/a3h) the disconnect steps command is used by the target to disconnect from the scsi bus. this command is exe- cuted in two steps. in the message in phase, the target sends two bytes of the save data pointers commands. following transmission, the target disconnects from the scsi bus. successful operation and disconnected bits are set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator then successful operation and service re- quest bits are set in the instreg, the command regis- ter (cmdreg) is cleared and disconnect steps com- mand terminates without disconnecting. terminate steps command (command code 24h/a4h) the terminate steps command is used by the target to disconnect from the scsi bus. this command is exe- cuted in three steps. while in status phase, the target first sends a 1 byte status message. following the status phase the target moves to the message in phase and sends another 1 byte message. lastly, the target disconnects from the scsi bus. the discon- nected bit is set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator, then successful operation and service request bits are set in the instreg, an inter- rupt is generated and the command register (cmdreg) is cleared and terminate steps command terminates without disconnecting. target command complete steps command (command code 25h/a5h) the target command complete steps command is used by the target to inform the initiator of a linked com- mand completion. this command consists of two steps. in the first step, the target sends one status byte to the initiator in the status phase. the target then sends one message byte to the initiator in the message in phase. the successful operation bit is set in the interrupt status register (instreg) upon command comple- tion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the command register (cmdreg) is cleared and target command complete steps com- mand terminates prematurely. disconnect command (command code 27h/a7h) the disconnect command is used by the target to dis- connect from the scsi bus. all scsi bus signals except rstc are released and the device returns to the dis- connected state. the rstc signal is driven active for about 25 micro seconds (depending on clock frequency and clock factor). interrupt is not generated to the micro- processor. receive message steps command (command code 28h/a8h) the receive message steps command is used by the target to request message bytes from the initiator. the target receives the message bytes from the initiator while the scsi bus is in the message out phase. the successful operation bit is set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the in- streg, the command register (cmdreg) is cleared, but if a parity error is detected, the device ignores the re- ceived message bytes until atn signal is deasserted, the successful operation bit is set in the instreg, and the cmdreg is cleared. receive commands command (command code 29h/a9h) the receive commands command is used by the target to request command bytes from the initiator. the target receives the command bytes from the initiator while the scsi bus is in the command phase. the successful operation bit is set in the interrupt status register (instreg) upon command completion. if atn signal is asserted by the initiator then successful operation and service request bits are set in the instreg, the command register (cmdreg) is cleared and the command terminates prematurely. if a parity error is detected, the device continues to receive command bytes until the transfer is complete. however, if the abort on command data/parity error (acdpe) bit in control register two (cntlreg2) bit is set, the command is terminated immediately. the parity error (pe) bit in the status register (statreg) is set and cmdreg is cleared. receive data command (command code 2ah/aah) the receive data command is used by the target to re- quest data bytes from the initiator. during this command the target receives the data bytes from the initiator while the scsi bus is in the data-out phase. the suc- cessful operation bit is set in the interrupt status regis- ter (instreg) upon command completion. if atn sig- nal is asserted by the initiator then successful opera- tion and service request bits are set in the instreg, the command register (cmdreg) is cleared and the command terminates prematurely. if a parity error is de- tected, the device continues to receive data bytes until the transfer is complete (abort on command/data par- ity error (acdpe) bit in control register two (cntlreg2) is reset). if the acdpe bit is set, the com- mand is terminated immediately. the parity error (pe) bit in the status register (statreg) is set and cmdreg is cleared.
p r e l i m i n a r y amd 41 am53cf94/am53cf96 receive command steps command (command code 2bh/abh) the receive command steps command is used by the target to request command information bytes from the initiator. during this command the target receives the command information bytes from the initiator while the scsi bus is in the command phase. the target device determines the command block length from the first byte. if an unknown length is re- ceived, the start transfer count register (stcreg) is loaded with five and the group code valid (gcv) bit in the status register (statreg) is reset. if a valid length is received, the stcreg is loaded with the appropriate value and the gcv bit in the statreg is set. if atn sig- nal is asserted by the initiator then the service request bit is set in the interrupt status register (instreg), and the command register (cmdreg) is cleared. if a parity error is detected, the command is terminated pre- maturely and the cmdreg is cleared. dma stop command (command code 04h/84h) the dma stop command is used by the target to allow the microprocessor to discontinue data transfers due to a lack of activity on the dma channel. this command is executed from the top of the command queue. if there is a queued command waiting execution, it will be over- written and the illegal operation error (ioe) bit in the status register (statreg) will be set. this command is cleared from the command queue once it is decoded. caution must be exercised when using this command. the following conditions must be true: n the dma stop command can be used only during dma target send data command or dma target receive data command execution. in both cases the dma controller and the esc must be in the idle state. n during a dma target send data command: the fifo is empty or the current fifo (cf 4:0) bits in the current fifo/internal state register (cfisreg) are zero. n during a dma synchronous target receive data command: the current transfer count register (ctcreg) is zero, (indicated by the count to zero (ctz) bit of the status register (statreg)), or the synchronous offset register (sofreg) has reached its maximum value (indicated by the synchronous offset flag (sof) bit of the internal state register (isreg)). n during a dma asynchronous target receive data command: the fifo is full (cf 4:0 set to 1 in the current fifo/internal state register (cfisreg)), or current transfer count register (ctcreg) is zero (indicated by the count to zero (ctz) bit of the status register (statreg)). when conditions are satisfied, the esc halts, asserts dreq, and then waits for the dma channel. if the esc halted during synchronous transfer, the ack pulses not received from the scsi bus remain outstanding. upon receipt of the dma stop command, the esc re- sets the dma interface and dreq pin, then terminates the command in progress. ongoing scsi sequences are completed as follows: n synch data send: completes when ctz bit in status register is 1. n synch data receive: when all outstanding ack s received, command completes n asynchronous data send: immediately completes n asynchronous data receive: immediately com- pletes. remaining data in fifo should be removed by microprocessor. access fifo command (command code 05h/85h) the host may issue the access fifo command follow- ing a target abort dma or abort due to parity error. this command will give the dma controller access to the data remaining in the fifo. the following shall be true depending on the status of the dae bit in cntrlreg2: dae=1: dreq will be asserted if the fifo has two or more bytes of data, and will deassert if the fifo contains one or zero bytes of data. dae=0: dreq will be asserted if the fifo is not empty, and will deassert when the fifo is empty. while dreq is asserted, the dma controller may read the data. this command is supported only in normal dma mode. idle state commands the idle state commands can be issued to the device only when the device is disconnected from the scsi bus. if these commands are issued to the device when it is logically connected to the scsi bus, the commands are ignored, and the device will generate an invalid command interrupt and clear the command register (cmdreg). reselect steps command (command code 40h/c0h) the reselect steps command is used by the target de- vice to reselect an initiator device. when this command is issued the device arbitrates for the control of the scsi bus. if the device wins arbitration, it reselects the initia- tor device and transfers a single byte identify message. before issuing this command the scsi timeout regis- ter (stimreg), the control register one (cntlreg1) and the scsi destination id register (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to one. if dma is not enabled, the single byte identify message must be loaded into the fifo before issuing this com- mand. this command will be terminated early if the scsi timeout register times out, or if sequence termi- nates normally, a successful operation interrupt will be issued. this command also resets the internal state register (isreg).
p r e l i m i n a r y amd 42 am53cf94/am53cf96 select without atn steps command (command code 41h/c1h) the select without atn steps command is used by the initiator to select a target. when this command is issued the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device and transfers the command descriptor block (cdb). before issuing this command the scsi timeout register (stimreg), the control register one (cntlreg1) and the scsi destination id regis- ter (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to the total length of the command. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this command will be terminated early if the scsi timeout register times out or if the target does not go to the command phase following the selection phase or if the target exits the command phase prematurely. a successful operation interrupt will be generated follow- ing normal command execution. select with atn steps command (command code 42h/c2h) the select with atn steps command is used by the in- itiator to select a target. when this command is issued the device arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device with the atn signal asserted and transfers the command descriptor block (cdb) and a one byte mes- sage. before issuing this command the scsi timeout register (stimreg), the control register one (cntlreg1) and the scsi destination id register (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to the total length of the command and mes- sage. if dma is not enabled, the data must be loaded into the fifo before issuing this command. this com- mand will be terminated early in the following situations: n the scsi timeout register times out n the target does not go to the message out phase following the selection phase n the target exits the message phase early n the target does not go to the command phase following the message out phase n the target exits the command phase early a successful operation/service request interrupt is generated when this command is completed success- fully. select with atn and stop steps command (command code 43h/c3h) the select with atn and stop steps command is used by the initiator to send messages with lengths other than 1 or 3 bytes. when this command is issued, the device executes the selection process, transfers the first mes- sage byte, then stops the sequence. atn is not deas- serted at this time, allowing the initiator to send addi- tional message bytes after the id message. to send these additional bytes, the initiator must write the trans- fer counter with the number of bytes which will follow, then issue an information transfer command. (note: the target is still in the message out phase when this com- mand is issued). atn will remain asserted until the transfer counter decrements to zero. the scsi timeout register (stimreg), control regis- ter one (cntlreg1), and the scsi destination id register (sdidreg) must be set to the proper values before beginning the initiator issues this command. this command will be terminated early if the stimreg times out or if the target does not go to the message out phase following the selection phase. enable selection/reselection command (command code 44h/c4h) the enable selection/reselection command is used by the target to respond to a bus-initiated selection or reselection. upon disconnecting from the bus the se- lection/reselection circuit is automatically disabled by device. this circuit has to be enabled for the device to respond to subsequent reselection attempts and the en- able selection/reselection command is issued to do that. this command is normally issued within 250 ms (select/reselect timeout) after the device disconnects from the bus. if dma is enabled the device loads the re- ceived data to the buffer memory, but if the dma is dis- abled, the received data stays in the fifo. disable selection/reselection command (command code 45h/c5h) the disable selection/reselection command is used by the target to disable response to a bus-initiated reselection. when this command is issued before a bus initiated selection or reselection is initiated, it resets the internal mode bits previously set by the enable se- lection/reselection command. the device also gener- ates a function complete interrupt to the processor. if however, this command is issued after a bus initiated selection/reselection has already begun the command is ignored since the command register (cmdreg) is held reset and all incoming commands are ignored. the device generates a selected or reselected interrupt when the sequence is complete. select with atn3 steps command (command code 46h/c6h) the select with atn3 steps command is used by the initiator to select a target. this command is similar to the select with atn steps command, except that it sends exactly three message bytes. when this com- mand is issued the esc arbitrates for the control of the scsi bus. when the device wins arbitration, it selects the target device with the atn signal asserted and transfers the command descriptor block (cdb) and three message bytes. before issuing this command the scsi timeout register (stimreg), the control regis- ter one (cntlreg1) and the scsi destination id reg- ister (sdidreg) must be set to the proper values. if dma is enabled, the start transfer count register (stcreg) must be set to the total length of the com- mand. if dma is not enabled, the data must be loaded
p r e l i m i n a r y amd 43 am53cf94/am53cf96 into the fifo before issuing this command. this com- mand will be terminated early in the following situations: n the scsi timeout register times out n the target does not go to the message out phase following the selection phase n the target removes command phase early n the target does not go to the command phase following the message out phase n the target exits the command out phase early a successful operation/service request interrupt is generated when this command is executed success- fully. reselect with atn3 steps command (command code 47h/c7h) the queue tag feature of the select with atn3 com- mand has been implemented in the reselection com- mand. therefore, a target reselecting an initiator can use the qtag feature of atn3 . following reselection, one message byte and 2 bytes qtag will be sent. the three message bytes must be loaded into the fifo be- fore this command is issued if dma is not enabled. general commands no operation command (command code 00h/80h) the no operation command administers no operation, therefore an interrupt is not generated upon completion. this command is issued following the reset device command to clear the command register (cmdreg). a no operation command in the dma mode may be used to verify the contents of the start transfer count register (stcreg). after the stcreg is loaded with the transfer count and a dma no operation command is issued, reading the current transfer count register (ctcreg) will give the transfer count value. clear fifo command (command code 01h/81h) the clear fifo command is used to initialize the fifo to the empty condition. the current fifo register (cfisreg) reflects the empty fifo status and the bot- tom of the fifo is set to zero. no interrupt is generated at the end of this command. reset device command (command code 02h/82h) the reset device command immediately stops any de- vice operation and resets all the functions of the device. it returns the device to the disconnected state and it also generates a hard reset. the reset device command re- mains on the top of the command register fifo hold- ing the device in the reset state until the no operation command is loaded. the no operation command serves to enable the command register. reset scsi bus command (command code 03h/83h) the reset scsi bus command forces the rstc signal active for a period of 25 m s, and drives the chip to the disconnected state. an interrupt is not generated upon command completion, however, if bit 6 is not disabled in control register one (cntlreg1), a scsi reset inter- rupt will be issued.
p r e l i m i n a r y amd 44 am53cf94/am53cf96 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature under bias C55 c to +125 c . . . . . . . . . . . . . . . . . . . v dd C0.5 v to +7.0 v . . . . . . . . . . . . . . . . . . . . . . . . . dc voltage applied to any pin C0.5 to (v dd + 0.5) v . . . . . . . . . . . . . . . . . input static discharge protection 4k v pin-to-pin . . . . (human body model: 100 pf at 1.5k w ) stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial devices ambient temperature (t a )0 c to +70 c . . . . . . . supply voltage (v dd ) 4.5 v to 5.5 v . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed.
p r e l i m i n a r y amd 45 am53cf94/am53cf96 dc operating characteristics i dds static supply current v dd max 4.0 ma i ddd dynamic supply current v dd max 30 ma i lu latch up current all i/o v lu 10 v C 100 +100 ma c capacitance all pins 10 pf v ih input high voltage all scsi inputs 2.0 v dd + 0.5 v v il input low voltage all scsi inputs v ss C 0.5 0.8 v v ihst input hysterisis all scsi inputs 4.5 v < v dd < 5.5 v 300 mv v oh output high voltage sd 7C0, sd pi oh = C 2 ma 2.4 v dd v v sol1 scsi output low voltage sd 7C0, sd pi ol = 4 ma v ss 0.4 v v sol2 scsi output low voltage sdc 7C0, sdc p, i ol = 48 ma v ss 0.5 v msg , c/d , i/o , atn , rstc , selc , bsyc , ackc and reqc i il input low leakage 0.0 v < v in < 2.7 v C10 +10 m a i ih input high leakage 2.7 v < v in < v dd C10 +10 m a i oz high impedance leakage 0 v < v out < v dd C10 +10 m a v ih input high voltage 2.0 v dd + 0.5 v v il input low voltage v ss C 0.5 0.8 v v oh output high voltage dma 15C0 and i oh = C 2 ma 2.4 v dd v dmap 1C0 ad 7C0 i oh = C 1 ma v ol output low voltage dma 15C0 and i ol = 4 ma v ss 0.4 v dmap 1C0 ad 7C0 i ol = 2 ma i il input low leakage dma 15C0, 0 v < v in < v il C 10 +10 m a dmap 1C0 and ad 7C0 i ih input high leakage dma 15C0, v ih < v in < v dd C10 +10 m a dmap 1C0 and ad 7C0 i oz high impedance leakage 0 v < v out < v dd C10 +10 m a v oh output high voltage dreq, isel, i oh = C 2 ma 2.4 v dd v tsel, reqc *, ackc * v ol output low voltage dreq, isel, i ol = 4 ma v ss 0.4 v tsel, reqc *, ackc * i oz high impedance leakage 0 v < v out < v dd C10 +10 m a * reqc and ackc in differential mode only. parameter symbol parameter description pin names test conditions min max unit scsi pins bidirectional pins output pins
p r e l i m i n a r y amd 46 am53cf94/am53cf96 dc operating characteristics (continued) parameter symbol parameter description pin names test conditions min max unit v ih input high voltage a 3-0, cs, rd, wr , 2.0 v dd + 0.5 v dmawr , clk, busmd 1C0, dack , reset, and dfmode v il input low voltage a 3-0, cs, rd, wr ,v ss +0.5 0.8 v dmawr , clk, busmd 1C0, dack , reset, and dfmode i il input low voltage a 3-0, cs, rd, wr , C10 +10 m a dmawr , clk, busmd 1C0, dack , reset, and dfmode i ih input high voltage a 3-0, cs, rd, wr , C10 +10 m a dmawr , clk, busmd 1C0, dack , reset, and dfmode input pins 0 < v in < v il v ih < v in < v dd switching test circuit v t i ol i oh c l 0 v from output under test 17348b-35 switching test waveforms true data outputs ad 7C0, dma 15C0, dmap1C0 all inputs 1.5 v 3.0 v 0.0 v hi-z outputs ad 7C0, dma 15C0, dmap1C0 0.8 v all open drain outputs and int sd 7C0, sd p, dreq, isel, tsel v oh v ol v ol +0.3 v v ol v ol v oh 2.0 v v oh C0.3 v 2.0 v 2.0 v 2.3 v 0.8 v 17348b-36 2.3 v 0.8 v
p r e l i m i n a r y amd 47 am53cf94/am53cf96 key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs
p r e l i m i n a r y amd 48 am53cf94/am53cf96 1t pwl clock pulse width low 0.4 t cp 0.6 t cp ns 2t cp clock period (1 ? clock frequency) 25 50 ns 3a t l synchronization latency 54.58 2 t cp ns 4t pwh clock pulse width high 0.4 t cp 0.6 t cp ns 1t pwl 1 clock pulse width low 14.58 0.65 t cp ns 2t cp clock period (1 ? clock frequency) 40 100 ns 3t l synchronization latency 54.58 t pwl + t cp ns 4t pwh 1 clock pulse width high 14.58 0.65 t cp ns parameter no. symbol parameter description test conditions min max unit parameter no. symbol parameter description test conditions min max unit clock input note: clock frequency range for fast clk disabled. = 10 mhz to 25 mhz for asynchronous transmission = 12 mhz to 25 mhz for synchronous transmission 1 for synchronous data transmissions, the following conditions must be true: 2t cp + t pwl > 97.92 ns 2t cp + t pwh > 97.92 ns fastclk disabled (control register three (0ch) bit 3=0) note: clock frequency range for fast clk enabled. = 20 mhz to 40 mhz for asynchronous transmission = 20 mhz to 40 mhz for synchronous transmission fastclk enabled (control register three (0ch) bit 3=1) clk 2 41 3 17348b-37 3a
p r e l i m i n a r y amd 49 am53cf94/am53cf96 6t s int to rd set up time 0 ns 7t pd rd to int delay 0 100 ns 8t pwl rd pulse width low 50 ns 9t pd rd to int delay t l ns parameter no. symbol parameter description test conditions min max unit int rd interrupt output 68 9 7 note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). parameter no. symbol parameter description test conditions min max unit reset input 5t pwh reset pulse width high 500 ns note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). reset 5 17348b-38 17348b-39
p r e l i m i n a r y amd 50 am53cf94/am53cf96 10 11 16 12 14 19 cs rd a 3C0 ad 7C0 dma 7C0 dmap 0 17 15 13 18 20 21 22 17348b-40 register read with non-multiplexed address data bus cs wr ad 7C0 dma 7C0 dmap 0 a 3C0 10 11 26 27 23 24 28 25 29 19 31 30 17348b-41 register write with non-multiplexed address data bus
p r e l i m i n a r y amd 51 am53cf94/am53cf96 10 t s address to cs set up time 0 ns 11 t h address to cs hold time 30 ns 12 t s cs to rd set up time 0 ns 13 t pd cs to data valid delay 65 ns 14 t pwl rd pulse width low 30 ns 15 t pd rd to data valid delay 30 ns 16 t h rd to cs hold time 0 ns 17 t z rd to data high impedance 30 ns 18 t h rd to data hold time 2 ns 19 t pwh cs pulse width high 30 ns 20 t s rd to cs set up time 40 ns 21 t h cs to data hold time 2 ns 22 t z cs to data high impedance 30 ns 23 t s cs to wr set up time 0 ns 24 t pwl wr pulse width low 30 ns 25 t s data to wr set up time 15 ns 26 t h wr to cs hold time 0 ns 27 t s wr to cs set up time 30 ns 28 t pwh wr pulse width high 40 ns 29 t h data to wr hold time 0 ns 30 t h cs to data hold 30 ns 31 t s data to cs setup time 10 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). register read/write with non-multiplexed address data bus
p r e l i m i n a r y amd 52 am53cf94/am53cf96 cs rd ad 7C0 ale 33 34 32 35 36 43 37 39 41 38 40 42 address address data data 46 47 17348b-42 register read with muliplexed address data bus 33 34 32 35 43 50 52 cs ad 7C0 ale wr 48 49 53 address data address data 51 57 54 17348b-43 register write with multiplexed address data bus
p r e l i m i n a r y amd 53 am53cf94/am53cf96 32 t pwh ale pulse width high 20 ns 33 t s address to ale set up time 10 ns 34 t h address to ale hold time 10 ns 35 t s ale to cs set up time 10 ns 36 t pd cs to data valid delay 65 ns 37 t s cs to rd set up time 0 ns 38 t pd rd to data valid delay 30 ns 39 t pwl rd pulse width low 30 ns 40 t h rd to data hold time 2 ns 41 t h rd to cs hold time 0 ns 42 t z rd to data high impedance 30 ns 43 t s cs to ale set up time 50 ns 44 parameter does not exist 45 parameter does not exist 46 t pd cs to data hold time 2 ns 47 t z cs to data high impedance 30 ns 48 t s cs to wr set up time 0 ns 49 t pwl wr pulse width low 30 ns 50 t s data to wr set up time 15 ns 51 t s wr to ale set up time 50 ns 52 t h data to wr hold time 0 ns 53 t h wr to cs hold time 0 ns 54 t h cs to data hold time 30 ns 55 parameter does not exist 56 parameter does not exist 57 t s data setup to cs 10 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). register read/write with multiplexed address data bus
p r e l i m i n a r y amd 54 am53cf94/am53cf96 58 62 59 60 64 dreq dack dma 15C0 dmap 1C0 61 66 65 63 17348b-44 dma read without byte control dma 15C0 dmap 1C0 dreq dack dmawr 58 62 59 60 64 69 71 68 70 73 63 72 74 75 17348b-45 dma write without byte control
p r e l i m i n a r y amd 55 am53cf94/am53cf96 58 t pd dack to dreq valid delay 30 ns 59 t p dack to dack period 95 ns 60 t pwl dack pulse width low 45 ns 61 t pd dack to data valid delay 30 ns 62 t pd dack to dreq valid delay 30 ns 63 t p dack to dack period t l +25 ns 64 t pwh dack pulse width high 12 ns 65 t z dack to data high impedance 25 ns 66 t h dack to data hold time 2 ns 67 parameter does not exist 68 t s dack to dmawr set up time 0 ns 69 t pwl dmawr pulse width low 30 ns 70 t s data to dmawr set up time 15 ns 71 t h dmawr to dack hold time 0 ns 72 t pwh dmawr pulse width high 25 ns 73 t h data to dmawr hold time 0 ns 74 t s data to dack set up time 10 ns 75 t h dack to data hold time 10 ns parameter no. symbol parameter description test conditions min max unit dma read/write without byte control note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b).
p r e l i m i n a r y amd 56 am53cf94/am53cf96 92 dma 15C0 dmap 1C0 dreq dack dmard as 0 bhe 76 87 77 78 89 80 83 79 81 84 82 88 86 85 91 93 17348b-46 dma read with byte control 76 87 77 78 89 95 98 88 dreq dack as 0 bhe dmawr dma 15C0 dmap 1C0 94 96 99 97 101 100 103 102 17348b-47 dma write with byte control
p r e l i m i n a r y amd 57 am53cf94/am53cf96 76 t pd dack to dreq valid delay 30 ns 77 t p dack to dack period 95 ns 78 t pwl dack pulse width low 45 ns 79 t s dack to dmard set up time 0 ns 80 t s bhe, as0 to dmard set up time 20 ns 81 t pwl dmard pulse width low 35 ns 82 t pd dmard to data valid delay 35 ns 83 t h bhe, as0 to dmard hold time 20 ns 84 t h dmard to dack hold time 0 ns 85 t z dmard to data high impedance 35 ns 86 t h dmard to data hold time 2 ns 87 t pd dack to dreq valid delay 30 ns 88 t p dack to dack period t l + 25 ns 89 t pwh dack pulse width high 12 ns 90 parameter does not exist 91 t pd dack to data valid delay 30 ns 92 t h dack to data hold time 2 ns 93 t z dack to data high impedance 25 ns 94 t s dack to dmawr set up time 0 ns 95 t s bhe, as0 to dmawr set up time 20 ns 96 t pwl dmawr pulse width low 30 ns 97 t s data to dmawr set up time 15 ns 98 t h bhe, as0 to dmawr hold time 20 ns 99 t h dmawr to dack hold time 0 ns 100 t pwh dmawr pulse width high 25 ns 101 t h data to dmawr hold time 0 ns 102 t h dack to data hold time 10 ns 103 t s data to dack set up time 10 ns parameter no. symbol parameter description test conditions min max unit dma read/write with byte control note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b).
p r e l i m i n a r y amd 58 am53cf94/am53cf96 dreq dack dma 15C0 dmap 1C0 rd 115 104 105 116 109 112 106 110 108 114 113 107 117 118 119 17348b-48 burst dma read without byte controlmodes 0 and 1 dreq dack dma 15C0 dmap 1C0 dmawr 115 104 105 116 121 124 120 122 123 125 126 17348b-49 burst dma write without byte controlmodes 0 and 1
p r e l i m i n a r y amd 59 am53cf94/am53cf96 104 t pd dack to dreq valid delay 30 ns 105 t pwl dack pulse width low 70 ns 106 t s dack to rd set up time 0 ns 107 t p rd to dack hold time 0 ns 108 t pd rd to data valid delay 55 ns 109 t pwh rd pulse width high 60 ns 110 t pwl rd pulse width low 70 ns 111 parameter does not exist 112 t pd rd to dreq valid delay 90 ns 113 t z rd to data high impedance 45 ns 114 t h rd to data hold time 2 ns 115 t pd dack to dreq valid delay 30 ns 116 t pwh dack pulse width high 60 ns 117 t pd dack to data valid delay 35 ns 118 t h dack to data hold time 2 ns 119 t z dack to data high impedance 25 ns 120 t s dack to dmawr set up time 0 ns 121 t pwh dmawr pulse width high 60 ns 122 t pwl dmawr pulse width low 70 ns 123 t s data to dmawr set up time 15 ns 124 t pd dmawr to dreq valid delay 90 ns 125 t h data to dmawr hold time 0 ns 126 t h dmawr to dack hold time 0 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). burst dma read/write mode 0, 1
p r e l i m i n a r y amd 60 am53cf94/am53cf96 dreq dack dma 15C0 dmap 1C0 dmard as 0 bhe 138 127 128 139 132 135 130 133 131 137 136 129 134 140 142 143 144 17348b-50 burst dma read with byte controlmode 2 dreq dack dma 15C0 dmap 1C0 dmawr as 0 bhe 138 127 128 139 147 150 145 148 152 151 146 149 153 17348b-51 burst dma write with byte controlmode 2
p r e l i m i n a r y amd 61 am53cf94/am53cf96 127 t pd dack to dreq valid delay 30 ns 128 t pwl dack pulse width low 70 ns 129 t s bhe, as0 to dmard set up time 20 ns 130 t s dack to dmard set up time 0 ns 131 t pd dmard to data valid delay 55 ns 132 t pwh dmard pulse width high 60 ns 133 t pwl dmard pulse width low 70 ns 134 t h bhe, as0 to dmard hold time 20 ns 135 t pd dmard to dreq valid delay 90 ns 136 t z dmard to data high impedance 45 ns 137 t h dmard to data hold time 2 ns 138 t pd dack to dreq valid delay 30 ns 139 t pwh dack pulse width high 60 ns 140 t h dmard to dack hold time 0 ns 141 parameter does not exist 142 t pd dack to data valid delay 35 ns 143 t h dack to data hold time 2 ns 144 t z dack to data high impendance 25 ns 145 t s dack to dmawr set up time 0 ns 146 t s bhe, as0 to dmawr set up time 20 ns 147 t pwh dmawr pulse width high 60 ns 148 t pwl dmawr pulse width low 70 ns 149 t h bhe, as0 to dmawr hold time 20 ns 150 t pd dmawr to dreq valid delay 90 ns 151 t h data to dmawr hold time 0 ns 152 t s data to dmawr set up time 15 ns 153 t h dmawr to dack hold time 0 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). burst dmaCmode 2
p r e l i m i n a r y amd 62 am53cf94/am53cf96 157 154 dreq dack dma 15C0 dmap 1C0 158 155 156 159 160 17348b-52 burst dma read without byte controlmode 3 dreq dack dma 15C0 dmap 1C0 dmawr/ 154 155 157 158 162 163 166 164 167 165 168 17348b-53 burst dma write without byte controlmode 3
p r e l i m i n a r y amd 63 am53cf94/am53cf96 154 t pd dack to dreq valid delay 30 ns 155 t pwl dack pulse width low 70 ns 156 t pd dack to data valid delay 35 ns 157 t pd dack to dreq valid delay 30 ns 158 t pwh dack pulse width high 60 ns 159 t z dack to data high impedance 25 ns 160 t h dack to data hold time 2 ns 161 parameter does not exist 162 t s dack to dmawr set up time 0 ns 163 t pwl dmawr pulse width low 70 ns 164 t s data to dmawr set up time 15 ns 165 t h dmawr to dack hold time 0 ns 166 t pwh dmawr pulse width high 60 ns 167 t h data to dmawr hold time 0 ns 168 t pd dack to dreq valid delay 90 ns parameter no. symbol parameter description test conditions min max unit burst dma mode 3 note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b).
p r e l i m i n a r y amd 64 am53cf94/am53cf96 169 t s data to ackc set up time 60 ns 170 t pd req to data delay 5 ns 171 t pd req to ackc delay 50 ns 172 t pd req to ackc delay 50 ns parameter no. symbol parameter description test conditions min max unit asynchronous initiator send note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). req ackc sdc 7C0 sdcp 170 169 171 172 single ended: 169 t s data to ackc set up time 70 ns 170 t pd req to data delay 5 ns 171 t pd req to ackc delay 25 ns 172 t pd req to ackc delay 30 ns parameter no. symbol parameter description test conditions min max unit differential: 17348b-54
p r e l i m i n a r y amd 65 am53cf94/am53cf96 parameter no. symbol parameter description test conditions min max unit 173 t pd req to ackc delay 25 ns 174 t pd req to ackc delay 30 ns 175 t s data to req set up time 0 ns 176 t h req to data hold time 18 ns parameter no. symbol parameter description test conditions min max unit 173 t pd req to ackc delay 50 ns 174 t pd req to ackc delay 50 ns 175 t s data to req set up time 0 ns 176 t h req to data hold time 18 ns asynchronous initiator receive note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). req ackc sd 7C0 sdp 173 174 175 176 differential: single ended: 17348b-55
p r e l i m i n a r y amd 66 am53cf94/am53cf96 ack reqc sd 7C0 sdp 178 177 179 180 17348b-56 asynchronous target send 177 t s data to reqc set up time 60 ns 178 t h ack to data hold time 5 ns 179 t pd ack to reqc delay 50 ns 180 t pd ack to reqc delay 45 ns parameter no. symbol parameter description test conditions min max unit single ended: 177 t s data to reqc set up time 70 ns 178 t h ack to data hold time 5 ns 179 t pd ack to reqc delay 30 ns 180 t pd ack to reqc delay 30 ns parameter no. symbol parameter description test conditions min max unit differential: note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b).
p r e l i m i n a r y amd 67 am53cf94/am53cf96 parameter no. symbol parameter description test conditions min max unit 181 t pd ack to reqc delay 50 ns 182 t pd ack to reqc delay 45 ns 183 t s data to ack set up time 0 ns 184 t h ack to data hold time 18 ns asynchronous target receive note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). single ended: differential: ack reqc sdc 7C0 sdcp 181 182 183 184 parameter no. symbol parameter description test conditions min max unit 181 t pd ack to reqc delay 30 ns 182 t pd ack to reqc delay 30 ns 183 t s data to ack set up time 0 ns 184 t h ack to data hold time 18 ns 17348b-57
p r e l i m i n a r y amd 68 am53cf94/am53cf96 185 t s ackc or reqc to data 55 ns set up time 186 t pwl reqc or ackc pulse width low 90 ns 187 t pwh reqc or ackc pulse width high 90 ns 188 t h ackc or reqc to data hold time 100 ns parameter no. symbol parameter description test conditions min max unit synchronous initiator target transmit note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b). * the minimum values have a wide range since they depend on the synchronization latency. the synchronization latency, in turn, depends on the operating frequency of the device. reqc ackc sdc 7C0 sdcp 185 186 187 188 normal scsi: (single ended) 185 t s ackc or reqc to data 25 ns set up time 186 t pwl reqc or ackc pulse width low 30 ns 187 t pwh reqc or ackc pulse width high 30 ns 188 t h ackc or reqc to data hold time 35 ns parameter no. symbol parameter description test conditions min max unit fast scsi: (single ended) 185 t s ackc or reqc to data 65 ns set up time 186 t pwl reqc or ackc pulse width low 96 ns 187 t pwh reqc or ackc pulse width high 96 ns 188 t h ackc or reqc to data hold time 110 ns parameter no. symbol parameter description test conditions min max unit normal scsi: (differential) 185 t s ackc or reqc to data 35 ns set up time 186 t pwl reqc or ackc pulse width low 40 ns 187 t pwh reqc or ackc pulse width high 40 ns 188 t h ackc or reqc to data hold time 45 ns parameter no. symbol parameter description test conditions min max unit fast scsi: (differential) 17348b-58
p r e l i m i n a r y amd 69 am53cf94/am53cf96 req ack sdc 7C0 sdcp 191 192 189 190 17348b-59 synchronous initiator target receive 189 t pwl req pulse width low 27 ns 189 t pwl ack pulse width low 20 ns 190 t pwh req pulse width high 20 ns 190 t pwh ack pulse width high 20 ns 191 t s data to req or ack set up time 5 ns 192 t h req or ack to data hold time 15 ns parameter no. symbol parameter description test conditions min max unit note: there is a one-to-one relationship between every amd and emulex parameter (refer to appendix b).
p r e l i m i n a r y amd 70 am53cf94/am53cf96 appendix a pin connection cross reference for am53cf94 pin# amd emulex 1 dmap0 dbp0 2v ss v ss 3 dma8 db8 4 dma9 db9 5 dma10 db10 6 dma11 db11 7 dma12 db12 8 dma13 db13 9 dma14 db14 10 dma15 db15 11 dmap1 dbp1 12 sd 0 sdi0n 13 sd 1 sdi1n 14 sd 2 sdi2n 15 sd 3 sdi3n 16 sd 4 sdi4n 17 sd 5 sdi5n 18 sd 6 sdi6n 19 sd 7 sdi7n 20 sd p sdipn 21 v dd v dd 22 v ss v ss 23 sdc 0 sdo0n 24 sdc 1 sdo1n 25 sdc 2 sdo2n 26 sdc 3 sdo3n 27 v ss v ss 28 sdc 4 sdo4n 29 sdc 5 sdo5n 30 sdc 6 sdo6n 31 sdc 7 sdo7n 32 sdc p sdopn 33 v ss v ss 34 selc selon 35 bsyc bsyon 36 reqc reqon 37 ackc ackon 38 v ss v ss 39 msg msgion 40 c/d cdion 41 i/o ioion 42 atn atnion pin# amd emulex 43 rstc rston 44 v ss v ss 45 sel selin 46 bsy bsyin 47 req reqin 48 ack ackin 49 rst rstin 50 busmd 1 mode 1 51 busmd 0 mode 0 52 int intn 53 reset reset 54 wr wrn 55 rd rdn 56 cs csn 57 aso [a0] a0/sa0 58 bhe [a1] a1/bhe 59 dmard [a2] a2/dbrdn 60 ale [a3] a3/ale 61 clk ck 62 v dd v dd 63 ad0 pad0 64 ad1 pad1 65 ad2 pad2 66 ad3 pad3 67 v ss v ss 68 ad4 pad4 69 ad5 pad5 70 ad6 pad6 71 ad7 pad7 72 dreq dreq 73 dack dackn 74 dmawr dbwrn 75 v ss v ss 76 v ss v ss 77 dma0 db0 78 dma1 db1 79 dma2 db2 80 dma3 db3 81 dma4 db4 82 dma5 db5 83 dma6 db6 84 dma7 db7
p r e l i m i n a r y amd 71 am53cf94/am53cf96 appendix a pin connection cross reference for am53cf96 pin# amd emulex 1 dack dackn 2 dmawr dbwrn 3nc nc 4 isel igs 5v ss v ss 6 tsel tgs 7v ss v ss 8 dma0 db0 9 dma1 db1 10 dma2 db2 11 dma3 db3 12 dma4 db4 13 dma5 db5 14 dma6 db6 15 dma7 db7 16 dmap0 dbp0 17 v ss v ss 18 v ss v ss 19 dma8 db8 20 dma9 db9 21 dma10 db10 22 dma11 db11 23 dma12 db12 24 dma13 db13 25 dma14 db14 26 dma15 db15 27 dmap1 dbp1 28 nc nc 29 sd 0 sdi0n 30 sd 1 sdi1n 31 sd 2 sdi2n 32 sd 3 sdi3n 33 sd 4 sdi4n 34 sd 5 sdi5n 35 sd 6 sdi6n 36 sd 7 sdi7n 37 sd p sdipn 38 v dd v dd 39 nc nc 40 v ss v ss 41 v ss v ss 42 sdc 0 sdo0n 43 sdc 1 sdo1n 44 sdc 2 sdo2n 45 sdc 3 sdo3n 46 v ss v ss 47 v ss v ss 48 sdc 4 sdo4n 49 sdc 5 sdo5n 50 sdc 6 sdo6n pin# amd emulex 51 sdc 7 sdo7n 52 sdc p sdopn 53 nc nc 54 v ss v ss 55 v ss v ss 56 selc selon 57 bsyc bsyon 58 reqc reqon 59 ackc ackon 60 v ss v ss 61 v ss v ss 62 msg msgion 63 c/d cdion 64 i/o ioion 65 atn atnion 66 rstc rston 67 v ss v ss 68 v ss v ss 69 sel selin 70 bsy bsyin 71 req reqin 72 ack ackin 73 rst rstin 74 busmd 1 mode 1 75 busmd 0 mode 0 76 int intn 77 reset reset 78 nc nc 79 wr wrn 80 rd rdn 81 cs csn 82 aso [a0] a0/sa0 83 bhe [a1] a1/bhe 84 dmard [a2] a2/dbrdn 85 ale [a3] a3/ale 86 clk ck 87 dfmode diffmn 88 v dd v dd 89 nc nc 90 ad0 pad0 91 ad1 pad1 92 ad2 pad2 93 ad3 pad3 94 v ss v ss 95 v ss v ss 96 ad4 pad4 97 ad5 pad5 98 ad6 pad6 99 ad7 pad7 100 dreq dreq
p r e l i m i n a r y amd 72 am53cf94/am53cf96 appendix b emulex to amd timing parameters cross reference amd parameter # clock input, reset input, interrupt output: 12 24 31 45 57 69 register interface timing: 110 211 333 434 532 635 743 819 9 12, 37 10 14, 39 11 16, 41 12 20 13 13, 36 14 15, 38 15 21, 46 (min) 22, 47 (max) 16 18, 40 (min) 17, 42 (max) 17 23, 48 18 24, 49 19 26, 53 20 27 21 28 22 51 23 25, 50 24 29, 52 25 31, 57 26 30, 54 amd parameter # dma interface timing: 1 58, 76 2 62, 87 3 64, 89 4 60, 78 5 59, 77 6 63, 88 780 883 979 10 81 11 84 12 none 13 61, 91 14 82 15 66, 92 (min) 65, 93 (max) 16 86 (min) 85 (max) 17 95 18 98 19 68, 94 20 69, 96 21 71, 99 22 72, 100 23 70, 97 24 73,101 25 74, 103 26 75, 102 alternate dma interface timing: 1 104, 127, 154 2 115, 138, 157 3 116, 139, 158 4 105, 128, 155 5 129 6 134 7 106, 130 8 110, 133 9 107, 140 10 112, 135 11 109, 132 12 none 13 117, 142, 156 14 108, 131 amd parameter # alternate dma interface timing: (continued) 15 118, 143, 160 (min) 119, 144, 159 (max) 16 114, 137 (min) 113, 136 (max) 17 146 18 149 19 120, 145, 162 20 122, 148, 163 21 126, 153, 165 22 124, 150, 168 23 121, 147, 166 24 123, 152, 164 25 125, 151, 167 asynchronous timing: 1 179, 181 2 180, 182 3 171, 173 4 172, 174 5 (reqon) 177 5 (ackon) 169 6 (reqin) 170 6 (ackin) 178 7 (reqin) 175 7 (ackin) 183 8 (reqin) 176 8 (ackin) 184 synchronous timing: 1 186 2 187 3 185 4 188 5 189 6 190 7 189 8 190 9 191 10 192 emulex parameter # emulex parameter # emulex parameter #
p r e l i m i n a r y amd 73 am53cf94/am53cf96 physical dimensions* pl 084 plastic leaded chip carrier (measured in inches) .050 ref .042 .048 1.150 1.156 1.185 1.195 1.150 1.156 1.185 1.195 .042 .056 .165 .180 .090 .130 .007 .013 1.000 ref .013 .021 1.090 1.130 .020 min .025 .045 09980b cg08 pl 084 8/14/92 c dc r top view side view .026 .032 * for reference only. bsc is an ansi standard for basic space centering.
p r e l i m i n a r y amd 74 am53cf94/am53cf96 physical dimensions* pqr100 plastic quad flatpack trimmed and formed (measured in millimeters) 0.22 0.38 13.90 14.10 17.10 17.30 18.85 ref 19.90 20.10 23.00 23.40 0.65 ref pin 1 i.d. 12.35 ref 2.60 3.00 3.35 max 0.70 0.90 top view side view 15590d bx 45 9/6/91 sg pqj 100 (plastic quad flat pack; trimmed and formed) (measured in millimeters) 0.25 min * for reference only. bsc is an ansi standard for basic space centering.
p r e l i m i n a r y amd 75 am53cf94/am53cf96 physical dimensions* pqr100 plastic quad flatpack with molded carrier ring (measured in millimeters) top view pin 1 i.d. 19.80 20.10 27.87 28.13 31.37 31.63 35.87 36.13 13.80 14.10 25.20 bsc 27.87 28.13 31.37 31.63 35.50 35.90 35.87 36.13 .65 nom .65 typ .65 pitch .45 typ 2.00 4.80 1.80 side view cb 48 6/25/92 sg 0.22 0.38 25.15 25.25 22.15 22.25 35.50 35.90 25.15 25.25 22.15 22.25 30 50 80 100 * for reference only. not drawn to scale. bsc is an ansi standard for basic space centering.
p r e l i m i n a r y amd 76 am53cf94/am53cf96 trademarks copyright ? 1993 advanced micro devices. all rights reserved. amd and am386 are registered trademarks of advanced micro devices, inc. glitch eater is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

▲Up To Search▲

Price & Availability of AM53CF96JCW

	To Download AM53CF96JCW Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .